Searched refs:Hwreg (Results 1 - 12 of 12) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUAsmUtils.h22 namespace Hwreg { // Symbolic names for the hwreg(...) syntax. namespace in namespace:llvm::AMDGPU
26 } // namespace Hwreg
H A DAMDGPUAsmUtils.cpp52 namespace Hwreg { namespace in namespace:llvm::AMDGPU
54 // This must be in sync with llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_/LAST_, see SIDefines.h.
84 } // namespace Hwreg
H A DAMDGPUBaseInfo.h459 namespace Hwreg { namespace in namespace:llvm::AMDGPU
484 } // namespace Hwreg
H A DAMDGPUBaseInfo.cpp710 namespace Hwreg { namespace in namespace:llvm::AMDGPU
762 } // namespace Hwreg
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIModeRegister.cpp200 .addImm(((Width - 1) << AMDGPU::Hwreg::WIDTH_M1_SHIFT_) |
201 (Offset << AMDGPU::Hwreg::OFFSET_SHIFT_) |
202 (AMDGPU::Hwreg::ID_MODE << AMDGPU::Hwreg::ID_SHIFT_));
246 if (((Dst & AMDGPU::Hwreg::ID_MASK_) >> AMDGPU::Hwreg::ID_SHIFT_) !=
247 AMDGPU::Hwreg::ID_MODE)
250 unsigned Width = ((Dst & AMDGPU::Hwreg::WIDTH_M1_MASK_) >>
251 AMDGPU::Hwreg::WIDTH_M1_SHIFT_) +
254 (Dst & AMDGPU::Hwreg
[all...]
H A DSIFrameLowering.cpp232 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_LO |
233 (31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_)));
236 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_HI |
237 (31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_)));
H A DAMDGPULegalizerInfo.cpp1194 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
1195 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
1197 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
1198 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
1200 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
1201 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
1202 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
2052 unsigned SPDenormModeBitField = AMDGPU::Hwreg::ID_MODE |
2053 (4 << AMDGPU::Hwreg
[all...]
H A DSIDefines.h313 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. namespace in namespace:llvm::SIInstrFlags::SISrcMods::SIOutMods::AMDGPU::VGPRIndexMode::AMDGPUAsmVariants::AMDGPU::AMDGPU::SendMsg
369 } // namespace Hwreg
H A DGCNHazardRecognizer.cpp128 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_;
815 return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS;
H A DSIISelLowering.cpp3139 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
3140 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1);
4678 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
4679 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
4681 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
4682 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
4684 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
4685 Offset << AMDGPU::Hwreg
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp1316 using namespace llvm::AMDGPU::Hwreg;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp855 case ImmTyHwreg: OS << "Hwreg"; break;
4994 using namespace llvm::AMDGPU::Hwreg;
5023 using namespace llvm::AMDGPU::Hwreg;
5043 using namespace llvm::AMDGPU::Hwreg;

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