Searched refs:Hi1 (Results 1 - 7 of 7) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp207 unsigned Hi1 = (Value >> 11) & 0x1; local
213 // Inst{7} = Hi1;
214 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp750 SDValue Hi1 = Node->getOperand(1); local
755 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp344 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1));
355 .add(Hi1)
367 .add(Hi1)
H A DAMDGPUISelDAGToDAG.cpp1018 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, local
1036 SDValue(Hi1, 0),
H A DSIISelLowering.cpp3998 SDValue Lo1, Hi1; local
3999 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4005 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
4019 SDValue Lo1, Hi1; local
4020 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4028 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2,
7533 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); local
7535 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp2610 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; local
2613 GetSplitVector(N->getOperand(1), Lo1, Hi1);
2619 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8375 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); local
8376 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
8380 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
8383 if (Hi0->isNullValue() && Hi1->isNullValue())

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