Searched refs:GPRArgRegs (Results 1 - 4 of 4) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; local
76 Reg = State.AllocateReg(GPRArgRegs);
H A DARMFastISel.cpp3055 static const MCPhysReg GPRArgRegs[] = { local
3062 unsigned SrcReg = GPRArgRegs[ArgNo];
H A DARMISelLowering.cpp152 static const MCPhysReg GPRArgRegs[] = { variable
2496 unsigned Reg = State->AllocateReg(GPRArgRegs);
2503 Reg = State->AllocateReg(GPRArgRegs);
2516 while (State->AllocateReg(GPRArgRegs))
2533 State->AllocateReg(GPRArgRegs);
3935 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3936 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4038 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4039 if (RegIdx != array_lengthof(GPRArgRegs))
4040 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegId
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3599 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2, local
3602 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
3603 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
3619 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);

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