Searched refs:DstR (Results 1 - 7 of 7) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | RDFCopy.cpp | 46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); local 48 assert(Register::isPhysicalRegister(DstR.Reg)); 51 if (TRI.getMinimalPhysRegClass(DstR.Reg) != 54 EM.insert(std::make_pair(DstR, SrcR));
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H A D | HexagonRDFOpt.cpp | 113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { 114 EM.insert(std::make_pair(DstR, SrcR));
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H A D | HexagonFrameLowering.cpp | 1607 Register DstR = MI->getOperand(0).getReg(); local 1609 if (!Hexagon::ModRegsRegClass.contains(DstR) || 1615 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR) 1665 Register DstR = MI->getOperand(0).getReg(); local 1675 // DstR = C2_tfrrp TmpR if DstR is a predicate register 1676 // DstR = A2_tfrrcr TmpR if DstR is a modifier register 1679 BuildMI(B, It, DL, HII.get(TfrOpc), DstR) 1732 Register DstR local 1835 Register DstR = MI->getOperand(0).getReg(); local 1913 Register DstR = MI->getOperand(0).getReg(); local 2356 Register DstR = MI.getOperand(0).getReg(); local [all...] |
H A D | HexagonExpandCondsets.cpp | 214 MachineBasicBlock::iterator At, unsigned DstR, 620 /// destination register DstR:DstSR, and using the predicate register from 625 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, 644 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) 647 .addReg(DstR, DstState, DstSR) 652 .addReg(DstR, DstState, DstSR) 623 genCondTfrFor(MachineOperand &SrcOp, MachineBasicBlock::iterator At, unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, bool PredSense, bool ReadUndef, bool ImpUse) argument
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H A D | HexagonGenInsert.cpp | 534 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR, 684 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, 686 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); 692 // The "source" register must be of the same class as DstR.
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H A D | HexagonSplitDouble.cpp | 1005 Register DstR = MI->getOperand(0).getReg(); local 1006 if (MRI->getRegClass(DstR) == DoubleRC) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 495 const Register DstR = Dst.getReg(); local 498 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) 508 const MachineOperand &Src = SrcR1 == DstR ? Index : Base; 510 BuildMI(MBB, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src); 517 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; 518 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR)
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