Searched refs:Dep (Results 1 - 25 of 42) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DBottleneckAnalysis.cpp154 const DependencyEdge::Dependency &DE = DepEdge.Dep;
244 uint64_t Cost = N.Cost + DepEdge.Dep.Cost;
368 const DependencyEdge::Dependency &Dep = DE->Dep;
372 if (Dep.Type == DependencyEdge::DT_REGISTER) {
376 MCIP.printRegName(FOS, Dep.ResourceOrRegID);
377 } else if (Dep.Type == DependencyEdge::DT_MEMORY) {
380 assert(Dep.Type == DependencyEdge::DT_RESOURCE &&
385 FOS << Tracker.resolveResourceName(Dep.ResourceOrRegID);
413 if (DE.Dep
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp35 static bool isHazard(const SDep &Dep) { argument
36 return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output;
178 for (SDep &Dep : AnchorSU.Preds) {
180 if (Dep.isWeak() || isHazard(Dep))
183 SUnit &DepSU = *Dep.getSUnit();
H A DScheduleDAGInstrs.cpp254 SDep Dep; local
256 Dep = SDep(SU, SDep::Artificial);
261 Dep = SDep(SU, SDep::Data, *Alias);
270 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
272 ST.adjustSchedDependency(SU, UseSU, Dep);
274 Dep.setLatency(0);
278 ST.adjustSchedDependency(SU, UseSU, Dep);
281 UseSU->addPred(Dep);
317 SDep Dep(SU, Kind, /*Reg=*/*Alias);
318 Dep
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H A DMachinePipeliner.cpp702 SDep Dep(Load, SDep::Barrier);
703 Dep.setLatency(1);
704 SU.addPred(Dep);
712 SDep Dep(Load, SDep::Barrier);
713 Dep.setLatency(1);
714 SU.addPred(Dep);
720 SDep Dep(Load, SDep::Barrier);
721 Dep.setLatency(1);
722 SU.addPred(Dep);
727 SDep Dep(Loa
1154 auto Dep = OutputDeps.find(BackEdge); local
2205 isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc) argument
2340 earliestCycleInChain(const SDep &Dep) argument
2363 latestCycleInChain(const SDep &Dep) argument
2412 const SDep &Dep = SU->Preds[i]; local
2437 const SDep &Dep = SU->Succs[i]; local
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H A DMachineTraceMetrics.cpp794 for (const DataDep &Dep : Deps) {
796 BlockInfo[Dep.DefMI->getParent()->getNumber()];
801 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
803 if (!Dep.DefMI->isTransient())
805 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp);
953 static bool pushDepHeight(const DataDep &Dep, const MachineInstr &UseMI,
957 // Adjust height by Dep.DefMI latency.
958 if (!Dep
[all...]
H A DScheduleDAG.cpp368 for (const SDep &Dep : SU.Preds) {
370 dumpNodeName(*Dep.getSUnit());
372 Dep.dump(TRI);
378 for (const SDep &Dep : SU.Succs) {
380 dumpNodeName(*Dep.getSUnit());
382 Dep.dump(TRI);
H A DImplicitNullChecks.cpp252 Optional<ArrayRef<MachineInstr *>::iterator> Dep; local
258 if (Dep == None) {
260 Dep = I;
267 return {true, Dep};
/freebsd-11-stable/contrib/llvm-project/clang/lib/Tooling/DependencyScanning/
H A DDependencyScanningTool.cpp59 for (const auto &Dep : Dependencies)
60 addDependency(Dep);
96 for (auto &&Dep : ClangModuleDeps)
97 Modules.push_back(Dep.first);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h80 PointerIntPair<SUnit *, 2, Kind> Dep; member in class:llvm::SDep
101 SDep() : Dep(nullptr, Data) {}
105 : Dep(S, kind), Contents() {
124 : Dep(S, Order), Contents(), Latency(0) {
385 SDep Dep(SU, SDep::Barrier);
388 Dep.setLatency(TrueMemOrderLatency);
389 return addPred(Dep);
466 if (Dep != Other.Dep)
468 switch (Dep
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H A DMachinePipeliner.h246 bool isBackedge(SUnit *Source, const SDep &Dep) { argument
247 if (Dep.getKind() != SDep::Anti)
249 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI();
252 bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc = true);
256 unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep) { argument
259 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti)
532 int earliestCycleInChain(const SDep &Dep);
536 int latestCycleInChain(const SDep &Dep);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/TableGen/
H A DMain.cpp75 for (const auto &Dep : Parser.getDependencies()) {
76 DepOut.os() << ' ' << Dep;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp320 SDep &Dep) const {
333 Dep.setLatency(0);
342 Dep.setLatency(0);
360 Dep.setLatency((unsigned)DLatency);
368 Dep.setLatency(0);
372 updateLatency(*SrcInst, *DstInst, Dep);
402 MachineInstr &DstInst, SDep &Dep) const {
403 if (Dep.isArtificial()) {
404 Dep.setLatency(1);
415 Dep
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H A DHexagonVLIWPacketizer.cpp929 auto &Dep = PacketSU->Succs[i]; local
930 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
931 Dep.getReg() == DepReg)
993 auto Dep = PacketSU->Succs[i]; local
998 if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
999 Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
1005 if (restrictingDepExistInPacket(*I, Dep.getReg()))
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/
H A DGIMatchTree.cpp97 for (auto &Dep : enumerate(MatchDag.predicate_edges())) {
98 PredicateDepIDs.insert(std::make_pair(Dep.value(), Dep.index()));
102 for (auto &Dep : enumerate(MatchDag.predicate_edges())) {
103 unsigned ID = PredicateIDs.lookup(Dep.value()->getPredicate());
104 UnsatisfiedPredDepsForPred[ID].set(Dep.index());
137 for (auto &Dep : enumerate(MatchDag.predicate_edges())) {
138 if (Dep.value()->getRequiredMI() == Instr &&
139 Dep.value()->getRequiredMO() == nullptr) {
141 DepsFor.value().reset(Dep
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DMemoryDependenceAnalysis.cpp877 MemDepResult Dep; local
880 Dep = getCallDependencyFrom(QueryCall, isReadonlyCall, ScanPos, DirtyBB);
884 Dep = MemDepResult::getNonLocal();
886 Dep = MemDepResult::getNonFuncLocal();
892 ExistingResult->setResult(Dep);
894 Cache.push_back(NonLocalDepEntry(DirtyBB, Dep));
898 if (!Dep.isNonLocal()) {
901 if (Instruction *Inst = Dep.getInst())
1018 MemDepResult Dep = local
1024 ExistingResult->setResult(Dep);
1264 MemDepResult Dep = GetNonLocalInfoForBlock(QueryInst, Loc, isLoad, BB, local
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H A DMemDepPrinter.cpp36 typedef std::pair<InstTypePair, const BasicBlock *> Dep; typedef in struct:__anon1635::MemDepPrinter
37 typedef SmallSetVector<Dep, 4> DepSet;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopLoadElimination.cpp190 for (const auto &Dep : *Deps) {
191 Instruction *Source = Dep.getSource(LAI);
192 Instruction *Destination = Dep.getDestination(LAI);
194 if (Dep.Type == MemoryDepChecker::Dependence::Unknown) {
202 if (Dep.isBackward())
208 assert(Dep.isForward() && "Needs to be a forward dependence");
H A DLoopInterchange.cpp117 std::vector<char> Dep; local
147 Dep.push_back(Direction);
150 Dep.push_back(Direction);
163 Dep.push_back(Direction);
166 while (Dep.size() != Level) {
167 Dep.push_back('I');
170 DepMatrix.push_back(Dep);
H A DLoopDistribute.cpp640 for (auto &Dep : Dependences)
641 if (Dep.isPossiblyBackward()) {
645 ++Accesses[Dep.Source].NumUnsafeDependencesStartOrEnd;
646 --Accesses[Dep.Destination].NumUnsafeDependencesStartOrEnd;
648 LLVM_DEBUG(Dep.print(dbgs(), 2, Instructions));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600Packetizer.cpp195 const SDep &Dep = SUJ->Succs[i]; variable
196 if (Dep.getSUnit() != SUI)
198 if (Dep.getKind() == SDep::Anti)
200 if (Dep.getKind() == SDep::Output)
H A DAMDGPUSubtarget.cpp720 SDep &Dep) const {
721 if (Dep.getKind() != SDep::Kind::Data || !Dep.getReg() ||
730 auto Reg = Dep.getReg();
740 Dep.setLatency(Lat);
743 auto Reg = Dep.getReg();
752 Dep.setLatency(Lat);
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/
H A DTemplateName.cpp76 TemplateName::TemplateName(DependentTemplateName *Dep) : Storage(Dep) {} argument
/freebsd-11-stable/contrib/llvm-project/clang/lib/Driver/
H A DXRayArgs.cpp222 for (const auto &Dep : ExtraDeps) {
224 ExtraDepOpt += Dep;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h765 for (auto Dep : *Deps)
766 Dependences[Dep.getSource(*LAI)].insert(Dep.getDestination(*LAI));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp503 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
505 Dep.setLatency(OpLatency);
507 computeOperandLatency(OpN, N, i, Dep);
508 ST.adjustSchedDependency(OpSU, SU, Dep);
511 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {

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