Searched refs:DPP (Results 1 - 9 of 9) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUAtomicOptimizer.cpp | 147 // we have DPP available on our subtarget, and the atomic operation is 32 221 // we have DPP available on our subtarget, and the atomic operation is 32 298 {Identity, V, B.getInt32(DPP::ROW_SHR0 | 1 << Idx), 302 // GFX9 has DPP row broadcast operations. 306 {Identity, V, B.getInt32(DPP::BCAST15), B.getInt32(0xa), 311 {Identity, V, B.getInt32(DPP::BCAST31), B.getInt32(0xc), 314 // On GFX10 all DPP operations are confined to a single row. To get cross- 325 {Identity, PermX, B.getInt32(DPP::QUAD_PERM_ID), 333 {Identity, Lane31, B.getInt32(DPP::QUAD_PERM_ID), 354 // GFX9 has DPP wavefron [all...] |
H A D | GCNHazardRecognizer.h | 76 int checkDPPHazards(MachineInstr *DPP);
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H A D | SIDefines.h | 42 DPP = 1 << 15, 232 DPP = 4 446 namespace DPP { namespace in namespace:llvm::SIInstrFlags::SISrcMods::SIOutMods::AMDGPU::VGPRIndexMode::AMDGPUAsmVariants::AMDGPU::AMDGPU::SendMsg::Hwreg::Swizzle 496 } // namespace DPP
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H A D | SIInstrInfo.h | 559 return MI.getDesc().TSFlags & SIInstrFlags::DPP; 563 return get(Opcode).TSFlags & SIInstrFlags::DPP;
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H A D | GCNHazardRecognizer.cpp | 603 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) { argument 607 // Check for DPP VGPR read after VALU VGPR write and EXEC write. 613 for (const MachineOperand &Use : DPP->uses()) {
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H A D | SIInstrInfo.cpp | 3700 using namespace AMDGPU::DPP;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.cpp | 308 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP) 699 using namespace AMDGPU::DPP; 807 using namespace llvm::AMDGPU::DPP;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 2664 (isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) || 2706 static const unsigned Variants[] = {AMDGPUAsmVariants::DPP}; 2712 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, AMDGPUAsmVariants::DPP 6433 using namespace AMDGPU::DPP; 6584 using namespace AMDGPU::DPP; 6771 using namespace llvm::AMDGPU::DPP;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.cpp | 259 using namespace llvm::AMDGPU::DPP; 283 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
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