Searched refs:DMA_WRITE (Results 1 - 4 of 4) sorted by relevance

/freebsd-11-stable/sys/dev/drm/
H A Dsavage_state.c47 DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
49 DMA_WRITE(scstart);
50 DMA_WRITE(scend);
73 DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
75 DMA_WRITE(drawctrl0);
76 DMA_WRITE(drawctrl1);
253 DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
819 DMA_WRITE(data->clear1.mask);
833 DMA_WRITE(clear_cmd);
836 DMA_WRITE(dev_pri
[all...]
H A Dmga_drv.h338 #define DMA_WRITE( offset, val ) \ macro
341 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04zx\n", \
349 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
353 DMA_WRITE( 1, val0 ); \
354 DMA_WRITE( 2, val1 ); \
355 DMA_WRITE( 3, val2 ); \
356 DMA_WRITE( 4, val3 ); \
H A Dsavage_drv.h466 DMA_WRITE(BCI_CMD_SET_REGISTER | \
474 DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
531 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) macro
/freebsd-11-stable/sys/arm/allwinner/
H A Da10_dmac.c88 #define DMA_WRITE(sc, reg, val) bus_write_4((sc)->sc_res[0], (reg), (val)) macro
92 DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val))
139 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0);
140 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0);
183 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta);
361 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen);
391 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen);
392 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta);

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