Searched refs:CondReg (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp786 unsigned &CondReg = CondRegs[Cond]; local
788 if (!CondReg && !InvCondReg)
789 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond);
791 if (CondReg)
792 return {CondReg, false};
841 unsigned &CondReg = CondRegs[Cond]; local
842 if (!CondReg)
843 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond);
852 .addReg(CondReg)
868 unsigned CondReg; local
894 unsigned CondReg; local
936 unsigned CondReg; local
1042 unsigned &CondReg = CondRegs[X86::COND_B]; local
1096 unsigned &CondReg = CondRegs[Cond]; local
[all...]
H A DX86FastISel.cpp2097 // Selects operate on i1, however, CondReg is 8 bits width and may contain
2102 unsigned CondReg = getRegForValue(Cond); local
2103 if (CondReg == 0)
2108 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
2109 unsigned KCondReg = CondReg;
2110 CondReg = createResultReg(&X86::GR32RegClass);
2112 TII.get(TargetOpcode::COPY), CondReg)
2114 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Kill=*/true,
2118 .addReg(CondReg, getKillRegStat
2320 unsigned CondReg = getRegForValue(Cond); local
[all...]
H A DX86InstructionSelector.cpp1408 const Register CondReg = I.getOperand(0).getReg(); local
1413 .addReg(CondReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInsertSkips.cpp348 const unsigned CondReg = TRI->getVCC(); local
361 if (A->modifiesRegister(CondReg, TRI)) {
362 if (!A->definesRegister(CondReg, TRI) || A->getOpcode() != And)
366 ReadsCond |= A->readsRegister(CondReg, TRI);
408 MI.killsRegister(CondReg, TRI))
423 MI.RemoveOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI));
H A DSIOptimizeExecMaskingPreRA.cpp198 const unsigned CondReg = Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; local
208 auto *And = TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister,
272 (CmpReg == CondReg &&
275 return MI.readsRegister(CondReg, TRI);
H A DAMDGPURegisterBankInfo.cpp835 Register CondReg; local
860 bool First = CondReg == AMDGPU::NoRegister;
862 CondReg = NewCondReg;
878 .addReg(CondReg);
879 CondReg = AndReg;
955 bool First = CondReg == AMDGPU::NoRegister;
957 CondReg = NewCondReg;
971 .addReg(CondReg);
972 CondReg = AndReg;
997 .addReg(CondReg, RegStat
1620 Register CondReg = MI.getOperand(0).getReg(); local
[all...]
H A DAMDGPUInstructionSelector.cpp1579 Register CondReg = CondOp.getReg();
1591 if (!isVCC(CondReg, *MRI)) {
1592 if (MRI->getType(CondReg) != LLT::scalar(32))
1610 if (!MRI->getRegClassOrNull(CondReg))
1611 MRI->setRegClass(CondReg, ConstrainRC);
1614 .addReg(CondReg);
H A DSIInstrInfo.cpp2048 static void preserveCondRegFlags(MachineOperand &CondReg, argument
2050 CondReg.setIsUndef(OrigCond.isUndef());
2051 CondReg.setIsKill(OrigCond.isKill());
2102 MachineOperand &CondReg = CondBr->getOperand(1); local
2103 CondReg.setIsUndef(Cond[1].isUndef());
2104 CondReg.setIsKill(Cond[1].isKill());
H A DAMDGPUMachineCFGStructurizer.cpp1896 Register CondReg = Cond[0].getReg();
1897 for (auto UI = MRI->use_begin(CondReg), E = MRI->use_end(); UI != E; ++UI) {
H A DAMDGPUISelDAGToDAG.cpp2069 unsigned CondReg = UseSCCBr ? (unsigned)AMDGPU::SCC : TRI->getVCC(); local
2096 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond);
H A DSIISelLowering.cpp3193 Register CondReg = MRI.createVirtualRegister(BoolRC); local
3212 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3220 .addReg(CondReg, RegState::Kill);
3222 MRI.setSimpleHint(NewExec, CondReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp891 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); local
892 if (CondReg == 0)
940 .addReg(CondReg);
1281 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not); local
1282 if (CondReg == 0)
1291 .addReg(CondReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp970 unsigned CondReg = getRegForValue(BI->getCondition()); local
971 if (CondReg == 0)
974 ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true);
1049 unsigned CondReg = getRegForValue(Cond); local
1051 if (!Src1Reg || !Src2Reg || !CondReg)
1058 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp776 auto CondReg = MIB->getOperand(1).getReg(); local
777 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
780 .addUse(CondReg)
H A DARMFastISel.cpp1623 unsigned CondReg = getRegForValue(I->getOperand(0)); local
1624 if (CondReg == 0) return false;
1650 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1653 .addReg(CondReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2512 unsigned CondReg = getRegForValue(BI->getCondition()); local
2513 if (!CondReg)
2526 unsigned CondReg = getRegForValue(BI->getCondition()); local
2527 if (CondReg == 0)
2540 = constrainOperandRegClass(II, CondReg, II.getNumDefs());
2752 unsigned CondReg = getRegForValue(Cond); local
2753 if (!CondReg)
2804 unsigned CondReg = getRegForValue(Cond); local
2805 if (!CondReg)
2810 CondReg
[all...]
H A DAArch64InstructionSelector.cpp983 const Register CondReg = I.getOperand(0).getReg(); local
985 MachineInstr *CCMI = MRI.getVRegDef(CondReg);
1500 const Register CondReg = I.getOperand(0).getReg(); local
1513 .addUse(CondReg)
1522 .addUse(CondReg)
2260 const Register CondReg = I.getOperand(1).getReg(); local
2271 .addUse(CondReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp790 unsigned CondReg = createResultReg(&PPC::CRRCRegClass); local
793 CondReg, PPCPred))
798 .addReg(CondReg).addMBB(TBB);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2662 Register CondReg = MI.getOperand(1).getReg(); local
2668 LLT CondTy = MRI.getType(CondReg);
2716 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
3683 Register CondReg = MI.getOperand(1).getReg();
3684 LLT CondTy = MRI.getType(CondReg);
3706 CondReg, Src1Regs[I], Src2Regs[I]);
3712 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);

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