Searched refs:CondCode (Results 1 - 25 of 82) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1034 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
1047 enum CondCode { enum in namespace:llvm::ISD
1080 inline bool isSignedIntSetCC(CondCode Code) {
1086 inline bool isUnsignedIntSetCC(CondCode Code) {
1093 inline bool isTrueWhenEqual(CondCode Cond) {
1100 inline unsigned getUnorderedFlavor(CondCode Cond) {
1106 CondCode getSetCCInverse(CondCode Operation, EVT Type);
1115 CondCode getSetCCInverse(CondCode Operatio
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H A DAnalysis.h108 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
112 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
117 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
H A DTargetLowering.h1173 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
1186 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1192 bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
2069 void setCondCodeAction(ISD::CondCode CC, MVT VT,
2624 /// Override the default CondCode to be used to test the result of the
2626 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2630 /// Get the CondCode that's to be used to test the result of the comparison
2632 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2775 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2806 /// The ISD::CondCode tha
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H A DSwitchLoweringUtils.h115 ISD::CondCode CC;
139 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCondCode.h10 enum CondCode { enum in namespace:llvm::LPCC
34 inline static StringRef lanaiCondCodeToString(LPCC::CondCode CC) {
73 inline static CondCode suffixToLanaiCondCode(StringRef S) {
74 return StringSwitch<CondCode>(S)
H A DLanaiInstrInfo.cpp123 static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC) {
351 SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4>
371 LPCC::CondCode CC;
372 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm();
375 LPCC::CondCode NewCC = getOppositeCondition(CC);
522 unsigned CondCode = MI.getOperand(3).getImm(); local
524 NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode)));
526 NewMI.addImm(CondCode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionOptimizer.cpp102 using CmpInfo = std::tuple<int, unsigned, AArch64CC::CondCode>;
112 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
114 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
229 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) {
243 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) {
274 AArch64CC::CondCode Cmp;
302 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode
305 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
309 CC = (AArch64CC::CondCode)(in
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H A DAArch64SpeculationHardening.cpp154 AArch64CC::CondCode &CondCode) const;
156 AArch64CC::CondCode &CondCode, DebugLoc DL) const;
188 AArch64CC::CondCode &CondCode) const {
211 // translate analyzeBranchCondCode to CondCode.
213 CondCode = AArch64CC::CondCode(analyzeBranchCondCode[0].getImm());
226 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode
225 insertTrackingCode( MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode &CondCode, DebugLoc DL) const argument
247 AArch64CC::CondCode CondCode; local
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H A DAArch64ConditionalCompares.cpp164 AArch64CC::CondCode HeadCmpBBCC;
170 AArch64CC::CondCode CmpBBTailCC;
270 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode
273 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
277 CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
H A DAArch64RedundantCopyElimination.cpp145 AArch64CC::CondCode CC = (AArch64CC::CondCode)CondBr.getOperand(0).getImm();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInfo.h24 enum CondCode { enum in namespace:llvm::ARCCC
H A DARCInstPrinter.cpp54 static const char *ARCCondCodeToString(ARCCC::CondCode CC) {
172 O << ARCCondCodeToString((ARCCC::CondCode)Op.getImm());
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MacroFusion.cpp27 X86::CondCode CC = X86::getCondFromBranch(MI);
H A DX86InstrInfo.h40 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
49 CondCode getCondFromBranch(const MachineInstr &MI);
52 CondCode getCondFromSETCC(const MachineInstr &MI);
55 CondCode getCondFromCMov(const MachineInstr &MI);
59 CondCode GetOppositeBranchCondition(CondCode CC);
62 unsigned getVPCMPImmForCond(ISD::CondCode CC);
H A DX86FlagsCopyLowering.cpp102 DebugLoc TestLoc, X86::CondCode Cond);
106 X86::CondCode Cond, CondRegArray &CondRegs);
341 static X86::CondCode getCondFromFCMOV(unsigned Opcode) {
754 X86::CondCode Cond = X86::getCondFromSETCC(MI);
773 DebugLoc TestLoc, X86::CondCode Cond) {
785 DebugLoc TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) {
813 X86::CondCode Cond = X86::COND_INVALID;
867 X86::CondCode Cond = X86::getCondFromCMov(CMovI);
893 X86::CondCode Cond = getCondFromFCMOV(CMovI.getOpcode());
935 X86::CondCode Con
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H A DX86CondBrFolding.cpp93 X86::CondCode BranchCode;
100 // A class that optimizes the conditional branch by hoisting and merge CondCode.
132 // Find a valid path that we can reuse the CondCode.
153 X86::CondCode CC = PredMBBInfo->BranchCode;
243 // Change the CondCode and BrInstr according to MBBInfo.
250 X86::CondCode CC = MBBInfo->BranchCode;
281 X86::CondCode CC;
309 X86::CondCode NewCC;
434 // Analyze instructions that generate CondCode and extract information.
484 X86::CondCode C
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H A DX86CmovConversion.cpp282 X86::CondCode FirstCC = X86::COND_INVALID, FirstOppCC = X86::COND_INVALID,
293 X86::CondCode CC = X86::getCondFromCMov(I);
655 X86::CondCode CC = X86::CondCode(X86::getCondFromCMov(MI));
656 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp37 enum CondCode { enum in namespace:llvm::XCore
133 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
146 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
157 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
212 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
233 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
289 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
298 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
406 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Con
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.h32 enum CondCode { enum in namespace:llvm::Mips
72 const char *MipsFCCToString(Mips::CondCode CC);
H A DMipsInstPrinter.cpp36 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
196 O << MipsFCCToString((Mips::CondCode)MO.getImm());
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp318 unsigned CondCode; local
320 CondCode = MSP430CC::COND_NE;
322 CondCode = MSP430CC::COND_E;
324 CondCode = MSP430CC::COND_LO;
326 CondCode = MSP430CC::COND_HS;
328 CondCode = MSP430CC::COND_N;
330 CondCode = MSP430CC::COND_GE;
332 CondCode = MSP430CC::COND_L;
334 CondCode = MSP430CC::COND_NONE;
338 if (CondCode
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp290 LPCC::CondCode CC =
291 static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm());
301 LPCC::CondCode CC =
302 static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm());
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h235 enum CondCode { // Meaning (integer) Meaning (floating-point) enum in namespace:llvm::AArch64CC
262 inline static const char *getCondCodeName(CondCode Code) {
284 inline static CondCode getInvertedCondCode(CondCode Code) {
287 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
294 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp102 static ARCCC::CondCode GetOppositeBranchCondition(ARCCC::CondCode CC) {
353 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm()));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp1053 LPCC::CondCode CondCode = local
1055 if (CondCode != LPCC::UNKNOWN) {
1059 MCConstantExpr::create(CondCode, getContext()), NameLoc, NameLoc));
1073 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); local
1074 if (CondCode != LPCC::UNKNOWN) {
1088 MCConstantExpr::create(CondCode, getContext()), NameLoc, NameLoc));

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