Searched refs:CmpVal (Results 1 - 14 of 14) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h217 Value *AlignedAddr, Value *CmpVal,
H A DRISCVISelLowering.cpp2900 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
2905 CmpVal = Builder.CreateSExt(CmpVal, Builder.getInt64Ty());
2914 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});
2898 emitMaskedAtomicCmpXchgIntrinsic( IRBuilder< &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2281 // a comparison of type Opcode between the AND result and CmpVal.
2286 uint64_t Mask, uint64_t CmpVal,
2305 if (CmpVal == 0) {
2311 if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <= Low) {
2317 if (EffectivelyUnsigned && CmpVal < Low) {
2325 if (CmpVal == Mask) {
2331 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
2337 if (EffectivelyUnsigned && CmpVal > Mas
2285 getTestUnderMaskCond(unsigned BitSize, unsigned CCMask, uint64_t Mask, uint64_t CmpVal, unsigned ICmpType) argument
3939 SDValue CmpVal = Node->getOperand(2); local
7293 Register CmpVal = MRI.createVirtualRegister(RC); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp736 Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
742 LLT CmpValTy = getMRI()->getType(CmpVal);
757 .addUse(CmpVal)
764 Register CmpVal, Register NewVal,
769 LLT CmpValTy = getMRI()->getType(CmpVal);
782 .addUse(CmpVal)
735 buildAtomicCmpXchgWithSuccess( Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO) argument
763 buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO) argument
H A DLegalizerHelper.cpp2062 Register CmpVal = MI.getOperand(3).getReg(); local
2064 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2066 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h967 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
970 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
978 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
984 Register Addr, Register CmpVal, Register NewVal,
987 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
991 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
997 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1002 Register CmpVal, Register NewVal,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2169 SDValue CmpVal = Mem->getOperand(2); local
2174 CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain()
2187 SDValue CmpVal = Mem->getOperand(2); local
2189 CmpVal, SRsrc, SOffset, Offset, SLC, Mem->getChain()
H A DAMDGPULegalizerInfo.cpp1783 Register CmpVal = MI.getOperand(2).getReg();
1790 LLT ValTy = MRI.getType(CmpVal);
1794 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp363 double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit; local
404 .addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, CmpVal)));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCompares.cpp4254 APInt CmpVal = APInt::getOneBitSet(TypeBits, ShAmt); local
4255 return new ICmpInst(NewPred, Xor, Builder.getInt(CmpVal));
5057 unsigned CmpVal = CI->countTrailingZeros(); local
5059 return new ICmpInst(NewPred, X, ConstantInt::get(X->getType(), CmpVal));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DAddressSanitizer.cpp1700 Value *CmpVal = Constant::getNullValue(ShadowTy); local
1704 Value *Cmp = IRB.CreateICmpNE(ShadowValue, CmpVal);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1743 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1741 emitMaskedAtomicCmpXchgIntrinsic( IRBuilder< &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1910 Register CmpVal = MI.getOperand(2).getReg(); local
1988 .addReg(CmpVal).addImm(MaskImm);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp5338 static bool isUndefOrEqual(int Val, int CmpVal) {
5339 return ((Val == SM_SentinelUndef) || (Val == CmpVal));
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