Searched refs:ArgRegs (Results 1 - 13 of 13) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp36 static const MCPhysReg ArgRegs[] = { local
40 const unsigned NumArgRegs = array_lengthof(ArgRegs);
42 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
46 // allocated yet. RegNum is actually an index into ArgRegs, which means we
49 State.AllocateReg(ArgRegs[RegNum]);
61 static const MCPhysReg ArgRegs[] = { local
65 const unsigned NumArgRegs = array_lengthof(ArgRegs);
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
74 State.AllocateReg(ArgRegs[RegNum + i]);
86 static const MCPhysReg ArgRegs[] local
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H A DPPCFastISel.cpp189 SmallVectorImpl<unsigned> &ArgRegs,
1375 SmallVectorImpl<unsigned> &ArgRegs,
1432 unsigned Arg = ArgRegs[VA.getValNo()];
1599 SmallVector<unsigned, 8> ArgRegs; local
1604 ArgRegs.reserve(NumArgs);
1630 ArgRegs.push_back(Arg);
1639 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1374 processCallArgs(SmallVectorImpl<Value*> &Args, SmallVectorImpl<unsigned> &ArgRegs, SmallVectorImpl<MVT> &ArgVTs, SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, SmallVectorImpl<unsigned> &RegArgs, CallingConv::ID CC, unsigned &NumBytes, bool IsVarArg) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp501 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); local
502 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
506 if (ArgRegs.size() == Idx)
511 (int)(RegSize * (ArgRegs.size() - Idx));
518 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
519 MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
522 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
H A DMipsISelLowering.cpp4372 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); local
4383 unsigned ArgReg = ArgRegs[FirstReg + I];
4432 unsigned ArgReg = ArgRegs[FirstReg + I];
4456 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); local
4457 unsigned Idx = State.getFirstUnallocated(ArgRegs);
4468 if (ArgRegs.size() == Idx)
4473 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4485 for (unsigned I = Idx; I < ArgRegs.size();
4487 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp521 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, local
524 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
525 if (FirstVAReg < array_lengthof(ArgRegs)) {
529 // There are (array_lengthof(ArgRegs) - FirstVAReg) registers which
532 MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4,
536 for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) {
539 RegInfo.addLiveIn(ArgRegs[i], VReg);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h316 /// \p ArgRegs is a list of lists of virtual registers containing each
318 /// ArgRegs[i]). For each argument, there will be one register for each
333 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp34 ArrayRef<ArrayRef<Register>> ArgRegs,
46 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{},
32 lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS, ArrayRef<Register> ResRegs, ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg, std::function<unsigned()> GetCalleeReg) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp222 SmallVectorImpl<Register> &ArgRegs,
1888 SmallVectorImpl<Register> &ArgRegs,
1955 Register Arg = ArgRegs[VA.getValNo()];
2226 SmallVector<Register, 8> ArgRegs; local
2230 ArgRegs.reserve(I->getNumOperands());
2245 ArgRegs.push_back(Arg);
2253 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2334 SmallVector<Register, 8> ArgRegs; local
2339 ArgRegs.reserve(arg_size);
2378 ArgRegs
1887 ProcessCallArgs(SmallVectorImpl<Value*> &Args, SmallVectorImpl<Register> &ArgRegs, SmallVectorImpl<MVT> &ArgVTs, SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, SmallVectorImpl<Register> &RegArgs, CallingConv::ID CC, unsigned &NumBytes, bool isVarArg) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1346 static const MCPhysReg ArgRegs[] = { local
1350 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
1351 if (FirstVAReg < array_lengthof(ArgRegs)) {
1355 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1365 RegInfo.addLiveIn(ArgRegs[i], VReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1990 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs); local
1991 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
2004 if (ArgRegs.size() == Idx) {
2008 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
2027 for (unsigned I = Idx; I < ArgRegs.size();
2030 RegInfo.addLiveIn(ArgRegs[I], Reg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp135 static const MCPhysReg ArgRegs[] = { local
139 const unsigned NumArgRegs = array_lengthof(ArgRegs);
140 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
142 // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
144 State.AllocateReg(ArgRegs[RegNum]);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp534 // Store remaining ArgRegs to the stack if this is a varargs function.
536 static const MCPhysReg ArgRegs[] = { local
539 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
540 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp3250 SmallVector<unsigned, 16> ArgRegs; local
3295 ArgRegs.push_back(ResultReg);
3327 unsigned ArgReg = ArgRegs[VA.getValNo()];

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