Searched refs:And0 (Results 1 - 6 of 6) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1614 Instruction *And0 = dyn_cast<Instruction>(I->getOperand(0));
1616 if (!And0 || !And1)
1618 if (And0->getOpcode() != Instruction::And ||
1621 if (And0->getOperand(1) != And1->getOperand(1))
1624 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)),
1625 And0->getOperand(1));
1746 Instruction *And0 = dyn_cast<Instruction>(Xor->getOperand(0));
1749 if (!And0 || And0->getOpcode() != Instruction::And)
1750 std::swap(And0, And
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2461 SDValue And0 = N->getOperand(0); local
2463 if (And0.hasOneUse() && And1.hasOneUse() &&
2464 isOpcWithIntImmediate(And0.getNode(), ISD::AND, Mask0Imm) &&
2473 std::swap(And0, And1);
2478 SDValue Dst = And0->getOperand(0);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 875 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
880 if (And0.getOpcode() != ISD::AND)
883 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
916 And0.getOperand(0));
956 And0->getOperand(0));
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 4062 auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask); local
4067 Or = MIRBuilder.buildOr(Dst, And0, And1);
4073 Or = MIRBuilder.buildOr(Dst, And0, And1);
4079 Or = MIRBuilder.buildOr(Dst, And0, And1);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 3979 SDValue And0 = And->getOperand(0); local
3997 if (!CurDAG->MaskedValueIsZero(And0, HighZeros))
4003 ReplaceNode(And, And0.getNode());
4009 SDValue NewAnd = CurDAG->getNode(ISD::AND, SDLoc(And), VT, And0, NewMask);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 6022 SDValue And0 = DAG.getNode(ISD::AND, DL, ShVT, Op1, BitWidthMinusOneC);
6024 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0),
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