Searched refs:And (Results 1 - 25 of 139) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/clang/lib/Analysis/
H A DThreadSafetyLogical.cpp44 case LExpr::And:
49 return RNeg ? RightOrOperator(cast<And>(RHS))
50 : RightAndOperator(cast<And>(RHS));
69 case LExpr::And:
74 return LNeg ? LeftAndOperator(cast<And>(LHS))
75 : LeftOrOperator(cast<And>(LHS));
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Basic/
H A DOperatorPrecedence.h35 And = 8, // & enumerator in enum:clang::prec::Level
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DGuardUtils.cpp87 auto *And = dyn_cast<Instruction>(Cond);
88 if (!And)
94 WC = &And->getOperandUse(0);
95 C = &And->getOperandUse(1);
101 WC = &And->getOperandUse(1);
102 C = &And->getOperandUse(0);
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyLogical.h25 And, enumerator in enum:clang::threadSafety::lexpr::LExpr::Opcode
68 class And : public BinOp { class in namespace:clang::threadSafety::lexpr
70 And(LExpr *LHS, LExpr *RHS) : BinOp(LHS, RHS, LExpr::And) {} function in class:clang::threadSafety::lexpr::And
72 static bool classof(const LExpr *E) { return E->kind() == LExpr::And; }
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMaskingPreRA.cpp208 auto *And = TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister,
210 if (!And || And->getOpcode() != AndOpc ||
211 !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
214 MachineOperand *AndCC = &And->getOperand(1);
218 AndCC = &And->getOperand(2);
221 } else if (And->getOperand(2).getReg() != ExecReg) {
225 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, MRI, LIS);
228 Cmp->getParent() != And
255 << *And); local
[all...]
H A DSILowerControlFlow.cpp225 MachineInstr *And = local
230 setImpSCCDefDead(*And, true);
261 LIS->ReplaceMachineInstrInMaps(MI, *And);
311 MachineInstr *And = local
317 LIS->InsertMachineInstrInMaps(*And);
373 MachineInstr *And = nullptr, *Or = nullptr; local
376 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg)
390 if (And)
391 LIS->InsertMachineInstrInMaps(*And);
H A DAMDGPUAtomicOptimizer.cpp124 case AtomicRMWInst::And:
181 Op = AtomicRMWInst::And;
257 case AtomicRMWInst::And:
258 return B.CreateBinOp(Instruction::And, LHS, RHS);
397 case AtomicRMWInst::And:
531 case AtomicRMWInst::And:
628 case AtomicRMWInst::And:
657 // And delete the original.
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h72 template <typename... Preds> struct And { struct in namespace:llvm::MIPatternMatch
80 struct And<Pred, Preds...> : And<Preds...> { struct in namespace:llvm::MIPatternMatch
82 And(Pred &&p, Preds &&... preds) function in struct:llvm::MIPatternMatch::And
83 : And<Preds...>(std::forward<Preds>(preds)...), P(std::forward<Pred>(p)) {
87 return P.match(MRI, src) && And<Preds...>::match(MRI, src);
109 template <typename... Preds> And<Preds...> m_all_of(Preds &&... preds) {
110 return And<Preds...>(std::forward<Preds>(preds)...);
/freebsd-11-stable/contrib/llvm-project/clang/lib/Basic/
H A DOperatorPrecedence.cpp59 case tok::amp: return prec::And;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp53 case Instruction::And:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAtomicRMW.cpp44 case AtomicRMWInst::And:
82 case AtomicRMWInst::And:
H A DInstCombineCompares.cpp1633 Instruction *InstCombiner::foldICmpAndShift(ICmpInst &Cmp, BinaryOperator *And, argument
1635 BinaryOperator *Shift = dyn_cast<BinaryOperator>(And->getOperand(0));
1663 // the And doesn't use any bits being shifted in. Normally these would
1686 Cmp.setOperand(1, ConstantInt::get(And->getType(), NewCst));
1688 And->setOperand(1, ConstantInt::get(And->getType(), NewAndCst));
1689 And->setOperand(0, Shift->getOperand(0));
1703 IsShl ? Builder.CreateLShr(And->getOperand(1), Shift->getOperand(1))
1704 : Builder.CreateShl(And->getOperand(1), Shift->getOperand(1));
1717 BinaryOperator *And,
1716 foldICmpAndConstConst(ICmpInst &Cmp, BinaryOperator *And, const APInt &C1) argument
1825 foldICmpAndConstant(ICmpInst &Cmp, BinaryOperator *And, const APInt &C) argument
2104 Value *And = Builder.CreateAnd(X, Mask, Shl->getName() + ".mask"); local
2116 Value *And = Builder.CreateAnd(X, Mask, Shl->getName() + ".mask"); local
2126 Value *And = Builder.CreateAnd(X, (~C).lshr(ShiftAmt->getZExtValue())); local
2134 Value *And = local
2249 Value *And = Builder.CreateAnd(X, Mask, Shr->getName() + ".mask"); local
2280 Value *And = Builder.CreateAnd(SRem->getOperand(0), MaskC); local
2984 Value *And = Builder.CreateAnd(BOp0, NotBOC); local
4267 Value *And = Builder.CreateAnd(Xor, Builder.getInt(AndVal), local
[all...]
H A DInstCombineCasts.cpp180 case Instruction::And:
355 case Instruction::And:
593 case Instruction::And:
732 Value *And = Builder.CreateAnd(Src, ConstantInt::get(SrcTy, 1)); local
733 return new ICmpInst(ICmpInst::ICMP_NE, And, Zero);
743 Value *And = Builder.CreateAnd(X, ConstantInt::get(SrcTy, MaskC)); local
744 return new ICmpInst(ICmpInst::ICMP_NE, And, Zero);
750 Value *And = Builder.CreateAnd(X, ConstantInt::get(SrcTy, MaskC)); local
751 return new ICmpInst(ICmpInst::ICMP_NE, And, Zero);
998 case Instruction::And
1158 Value *And = Builder.CreateAnd(A, AndConst, CSrc->getName() + ".mask"); local
[all...]
H A DInstCombineAndOrXor.cpp916 /// And X is checking that some bit in that same mask is zero.
931 assert(CxtI.getOpcode() == Instruction::And);
981 // And the other icmp needs to be decomposable into a bit test.
1416 assert((Opcode == Instruction::And || Opcode == Instruction::Or) &&
1428 FCmpInst::Predicate NanPred = Opcode == Instruction::And ? FCmpInst::FCMP_ORD
1461 assert((Opcode == Instruction::And || Opcode == Instruction::Or) &&
1465 Opcode = (Opcode == Instruction::And) ? Instruction::Or : Instruction::And;
1583 Value *Res = LogicOpc == Instruction::And ? foldAndOfICmps(ICmp0, ICmp1, I)
1595 if (Value *R = foldLogicOfFCmps(FCmp0, FCmp1, LogicOpc == Instruction::And))
1681 narrowMaskedBinOp(BinaryOperator &And) argument
1766 Value *And = Builder.CreateAnd(X, Op1); local
1780 Value *And = Builder.CreateAnd(X, ConstantInt::get(I.getType(), local
1839 auto *And = Builder.CreateAnd(BinOp, TruncC2); local
3080 Value *And = Builder.CreateAnd(X, ConstantExpr::getNot(C2)); local
[all...]
H A DInstCombineShifts.cpp243 // And compute the mask as usual: ~(-1 << (SumOfShAmts))
281 // And compute the mask as usual: (-1 l>> (NumHighBitsToClear))
316 return BinaryOperator::Create(Instruction::And, NewShift, NewMask);
515 case Instruction::And:
590 Value *And = Builder.CreateAnd(InnerShift->getOperand(0), local
592 if (auto *AndI = dyn_cast<Instruction>(And)) {
596 return And;
632 case Instruction::And:
677 case Instruction::And:
749 Value *And local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DTruncInstCombine.cpp53 case Instruction::And:
115 case Instruction::And:
346 case Instruction::And:
H A DAggressiveInstCombine.cpp246 Value *And = Builder.CreateAnd(MOps.Root, Mask); local
247 Value *Cmp = MatchAllBitsSet ? Builder.CreateICmpEQ(And, Mask)
248 : Builder.CreateIsNotNull(And);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstruction.h176 return Opcode == And || Opcode == Or || Opcode == Xor;
483 /// In LLVM, the Add, Mul, And, Or, and Xor operators are associative.
487 return Opcode == And || Opcode == Or || Opcode == Xor ||
503 case And: case Or: case Xor:
514 /// In LLVM, the And and Or operators are idempotent.
518 return Opcode == And || Opcode == Or;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandReductions.cpp42 return Instruction::And;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp103 (LI->getOpcode() == Instruction::And ||
297 case Instruction::And:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp886 // And for the inverse:
985 case Instruction::And:
1040 Value *And = IRBuilder<>(In).CreateAnd(T->getOperand(0), Mask); local
1041 T->replaceAllUsesWith(And);
1237 case Instruction::And:
1272 case Instruction::And:
1580 case Instruction::And:
1597 case Instruction::And:
1618 if (And0->getOpcode() != Instruction::And ||
1619 And1->getOpcode() != Instruction::And)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h112 And, member in class:llvm::X86::FirstMacroFusionInstKind
180 return FirstMacroFusionInstKind::And;
335 case X86::FirstMacroFusionInstKind::And:
615 /// to specify a memory source, but doesn't use the middle field. And has
655 /// to specify a register source, but doesn't use the middle field. And has
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCExpr.h427 And, ///< Bitwise and. enumerator in enum:llvm::MCBinaryExpr::Opcode
474 return create(And, LHS, RHS, Ctx);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1246 SDValue And = N->getOperand(0); local
1247 unsigned N0Opc = And.getMachineOpcode();
1252 And.getOperand(0),
1253 And.getOperand(1));
1269 SDValue Ops[] = { And.getOperand(1),
1270 And.getOperand(2),
1271 And.getOperand(3),
1272 And.getOperand(4),
1273 And.getOperand(5),
1274 And
1294 SDValue And = N->getOperand(0); local
1650 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); local
2016 SDValue And = N.getOperand(0); local
3952 shrinkAndImmediate(SDNode *And) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/AST/
H A DStmtVisitor.h135 BINOP_FALLBACK(And) BINOP_FALLBACK(Xor) BINOP_FALLBACK(Or)

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