Searched refs:v8i1 (Results 1 - 6 of 6) sorted by relevance

/freebsd-10.3-release/contrib/llvm/include/llvm/CodeGen/
H A DValueTypes.h65 v8i1 = 15, // 8 x i1 enumerator in enum:llvm::MVT::SimpleValueType
269 case v8i1 :
326 case v8i1 :
379 case v8i1: return 8;
507 if (NumElements == 8) return MVT::v8i1;
/freebsd-10.3-release/contrib/llvm/lib/IR/
H A DValueTypes.cpp133 case MVT::v8i1: return "v8i1";
201 case MVT::v8i1: return VectorType::get(Type::getInt1Ty(Context), 8);
/freebsd-10.3-release/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp414 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
427 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
442 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
443 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
H A DX86ISelLowering.cpp1309 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1375 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1379 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1556 case 8: return MVT::v8i1;
2225 else if (RegVT == MVT::v8i1)
5703 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5797 if (VT == MVT::v8i1) {
16386 /// Extract one bit from mask vector, like v16i1 or v8i1
[all...]
/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp404 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
407 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
/freebsd-10.3-release/contrib/llvm/utils/TableGen/
H A DCodeGenTarget.cpp74 case MVT::v8i1: return "MVT::v8i1";

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