Searched refs:mmio_base (Results 1 - 8 of 8) sorted by relevance
/freebsd-10.3-release/sys/dev/drm2/i915/ |
H A D | intel_ringbuffer.h | 14 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) 15 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) 17 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) 18 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) 20 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) 21 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) 23 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) 24 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) 26 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) 27 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), va 41 u32 mmio_base; member in struct:intel_ring_buffer [all...] |
H A D | intel_ringbuffer.c | 281 RING_ACTHD(ring->mmio_base) : ACTHD; 785 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 787 mmio = RING_HWS_PGA(ring->mmio_base); 1354 ring->mmio_base = RENDER_RING_BASE; 1420 ring->mmio_base = RENDER_RING_BASE; 1485 ring->mmio_base = GEN6_BSD_RING_BASE; 1503 ring->mmio_base = BSD_RING_BASE; 1532 ring->mmio_base = BLT_RING_BASE;
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H A D | i915_irq.c | 2471 = I915_READ(RING_SYNC_0(ring->mmio_base)); 2473 = I915_READ(RING_SYNC_1(ring->mmio_base)); 2477 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); 2478 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); 2479 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); 2480 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); 2481 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 2496 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
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H A D | i915_reg.h | 127 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 128 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 129 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 518 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
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H A D | intel_pm.c | 2380 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
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/freebsd-10.3-release/sys/dev/drm/ |
H A D | savage_bci.c | 566 unsigned long mmio_base, fb_base, fb_size, aperture_base; local 581 mmio_base = fb_base + SAVAGE_FB_SIZE_S3; 609 mmio_base = drm_get_resource_start(dev, 0); 629 mmio_base = drm_get_resource_start(dev, 0); 638 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
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H A D | mga_dma.c | 414 dev_priv->mmio_base = drm_get_resource_start(dev, 1); 723 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
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H A D | mga_drv.h | 119 u32 mmio_base; /**< Bus address of base of MMIO. */ member in struct:drm_mga_private
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