Searched refs:XOR (Results 1 - 25 of 100) sorted by relevance

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/freebsd-10.3-release/contrib/unbound/compat/
H A Dchacha_private.h41 #define XOR(v,w) ((v) ^ (w)) macro
46 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
47 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
48 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
49 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
167 x0 = XOR(x0,U8TO32_LITTLE(m + 0));
168 x1 = XOR(x1,U8TO32_LITTLE(m + 4));
169 x2 = XOR(x2,U8TO32_LITTLE(m + 8));
170 x3 = XOR(x3,U8TO32_LITTLE(m + 12));
171 x4 = XOR(x
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/freebsd-10.3-release/crypto/openssh/
H A Dchacha.c42 #define XOR(v,w) ((v) ^ (w)) macro
47 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
48 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
49 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
50 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
167 x0 = XOR(x0,U8TO32_LITTLE(m + 0));
168 x1 = XOR(x1,U8TO32_LITTLE(m + 4));
169 x2 = XOR(x2,U8TO32_LITTLE(m + 8));
170 x3 = XOR(x3,U8TO32_LITTLE(m + 12));
171 x4 = XOR(x
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/freebsd-10.3-release/crypto/openssh/openbsd-compat/
H A Dchacha_private.h41 #define XOR(v,w) ((v) ^ (w)) macro
46 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
47 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
48 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
49 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
167 x0 = XOR(x0,U8TO32_LITTLE(m + 0));
168 x1 = XOR(x1,U8TO32_LITTLE(m + 4));
169 x2 = XOR(x2,U8TO32_LITTLE(m + 8));
170 x3 = XOR(x3,U8TO32_LITTLE(m + 12));
171 x4 = XOR(x
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/freebsd-10.3-release/usr.bin/xlint/lint1/
H A Dop.h88 XOR, enumerator in enum:__anon12517
H A Dtree.c149 { XOR, { 1,0,1,0,0,1,1,0,1,0,0,0,1,0,0,1,0,
1161 case XOR:
2014 if (op == ORASS || op == OR || op == XOR) {
2841 case XOR:
3601 case XOR:
3960 case XOR:
3965 } else if (lop == AND || lop == XOR) {
3972 } else if (rop == AND || rop == XOR) {
/freebsd-10.3-release/contrib/llvm/lib/Target/R600/
H A DAMDILISelLowering.cpp411 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
519 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
522 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
528 r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
534 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
617 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
620 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
635 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
/freebsd-10.3-release/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h295 AND, OR, XOR, enumerator in enum:llvm::ISD::NodeType
/freebsd-10.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp66 // Implement vselect in terms of XOR, AND, OR when blend is not supported
207 case ISD::XOR:
581 // using XOR AND OR. The selector bit is broadcasted.
595 // AND,OR,XOR, we will have to scalarize the op.
600 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
627 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
656 // Implement VSELECT in terms of XOR, AND, OR
667 // AND,OR,XOR, we will have to scalarize the op.
670 // This operation also isn't safe with AND, OR, XOR when the boolean
674 TLI.getOperationAction(ISD::XOR, V
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H A DTargetLowering.cpp288 case ISD::XOR:
294 if (Op.getOpcode() == ISD::XOR &&
491 case ISD::XOR:
539 // for XOR, we prefer to force bits to 1 if they will make a -1.
1390 if ((N0.getOpcode() == ISD::XOR ||
1392 N0.getOperand(0).getOpcode() == ISD::XOR &&
1404 if (N0.getOpcode() == ISD::XOR)
1408 N0.getOperand(0).getOpcode() == ISD::XOR);
1425 if ((Op0.getOpcode() == ISD::XOR) &&
1707 N0.getOpcode() == ISD::XOR) {
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H A DDAGCombiner.cpp1147 case ISD::XOR: return visitXOR(N);
1228 case ISD::XOR:
1675 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1762 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
2382 // For each of OP in AND/OR/XOR:
3454 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3457 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3462 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3491 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3503 LHS = DAG.getNode(ISD::XOR, SDLo
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H A DFastISel.cpp368 // MVT::i1 is special. Allow AND, OR, or XOR because they
372 ISDOpcode == ISD::XOR))
919 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
1017 return SelectBinaryOp(I, ISD::XOR);
H A DSelectionDAGBuilder.h705 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
/freebsd-10.3-release/contrib/gcc/
H A Dsimplify-rtx.c427 if (GET_CODE (op) == XOR
431 return simplify_gen_binary (XOR, mode, XEXP (op, 0), temp);
439 return simplify_gen_binary (XOR, mode, XEXP (op, 0), temp);
590 if (GET_CODE (op) == XOR
1395 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
1616 && GET_CODE (op0) == XOR
1620 return simplify_gen_binary (XOR, mode, XEXP (op0, 0),
1621 simplify_gen_binary (XOR, mode, op1,
2094 case XOR:
2106 /* Canonicalize XOR o
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H A Dcombine.c4339 || code == AND || code == IOR || code == XOR)
4350 || code == AND || code == IOR || code == XOR
4545 if (GET_CODE (XEXP (x, 0)) == XOR
4713 return simplify_gen_binary (XOR, mode,
5055 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5064 || GET_CODE (t) == XOR)
5071 || GET_CODE (XEXP (t, 0)) == XOR
5090 || GET_CODE (XEXP (t, 0)) == XOR)
5107 || GET_CODE (XEXP (t, 0)) == XOR
5126 || GET_CODE (XEXP (t, 0)) == XOR)
[all...]
/freebsd-10.3-release/contrib/gdb/gdb/
H A Dada-lex.l211 xor { return XOR; }
H A Dp-exp.y216 %left XOR
427 exp : exp XOR exp
1036 {"xor", XOR, BINOP_END}
H A Dada-exp.y188 %left _AND_ OR XOR THEN ELSE
458 exp : exp XOR exp /* Fix for Ada elementwise XOR */
H A Dada-exp.c73 XOR = 275, enumerator in enum:yytokentype
121 #define XOR 275 macro
532 "THEN", "XOR", "OR", "_AND_", "'='", "'<'", "'>'", "DOTDOT", "IN",
H A Dp-exp.c76 XOR = 278, enumerator in enum:yytokentype
112 #define XOR 278 macro
488 "FALSEKEYWORD", "','", "ABOVE_COMMA", "ASSIGN", "NOT", "OR", "XOR",
2361 {"xor", XOR, BINOP_END}
/freebsd-10.3-release/libexec/rtld-elf/sparc64/
H A Dreloc.c522 #define XOR 0x82c06000 /* xor %g1, 0, %g1 */ macro
669 where[2] = XOR | ((~target) & 0x00001fff);
742 where[2] = XOR | (((~offset) >> 12) & 0x00001fff);
/freebsd-10.3-release/contrib/gcclibs/libcpp/include/
H A Dcpplib.h71 OP(XOR, "^") \
/freebsd-10.3-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp468 case ISD::XOR:
/freebsd-10.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp100 setTargetDAGCombine(ISD::XOR);
190 setOperationAction(ISD::XOR, Ty, Legal);
546 if (N->getOpcode() != ISD::XOR)
992 case ISD::XOR:
1508 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1516 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
2013 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2016 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
/freebsd-10.3-release/contrib/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp321 case X86ISD::XOR:
328 case ISD::XOR: {
1596 XOR, enumerator in enum:AtomicOpc
1792 Op = XOR;
2171 case ISD::XOR: {
2193 // This only matters for OR and XOR, AND is unaffected.
2224 case ISD::XOR: Op = X86::XOR32ri8; break;
2235 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
H A DX86ISelLowering.cpp895 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
896 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
897 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
898 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
1008 setOperationAction(ISD::XOR, VT, Promote);
1009 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1404 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1407 setOperationAction(ISD::XOR, MV
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