/freebsd-10.3-release/contrib/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 32 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) 40 if (MF->getTarget().getRegisterInfo() != TRI) { 41 TRI = MF->getTarget().getRegisterInfo(); 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 43 unsigned NumPSets = TRI->getNumRegPressureSets(); 50 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); 55 CSRNum.resize(TRI->getNumRegs(), 0); 57 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 101 unsigned Cost = TRI->getCostPerUse(PhysReg); 120 unsigned Cost = TRI [all...] |
H A D | LiveRegMatrix.cpp | 50 TRI = MF.getTarget().getRegisterInfo(); 55 unsigned NumRegUnits = TRI->getNumRegUnits(); 73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 74 << " to " << PrintReg(PhysReg, TRI) << ':'); 78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 79 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI)); 88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) 89 << " from " << PrintReg(PhysReg, TRI) << ':'); 91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 92 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI)); [all...] |
H A D | AllocationOrder.cpp | 34 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); local 36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); 43 dbgs() << ' ' << PrintReg(Hints[I], TRI);
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H A D | RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI; member in class:llvm::CoalescerPair 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | TargetRegisterInfo.cpp | 43 else if (TRI && Reg < TRI->getNumRegs()) 44 OS << '%' << TRI->getName(Reg); 48 if (TRI) 49 OS << ':' << TRI->getSubRegIndexName(SubIdx); 56 // Generic printout when TRI is missing. 57 if (!TRI) { 63 if (Unit >= TRI->getNumRegUnits()) { 69 MCRegUnitRootIterator Roots(Unit, TRI); 71 OS << TRI 161 firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI) argument [all...] |
H A D | RegAllocBase.h | 62 const TargetRegisterInfo *TRI; member in class:llvm::RegAllocBase 69 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
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H A D | MachineCopyPropagation.cpp | 35 const TargetRegisterInfo *TRI; member in class:__anon2274::MachineCopyPropagation 68 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 77 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR) 114 const TargetRegisterInfo *TRI) { 118 if (TRI->isSubRegister(SrcSrc, Def)) { 120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); 123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); 164 isNopCopy(CopyMI, Def, Src, TRI)) { 182 I->clearRegisterKills(Def, TRI); 192 for (MCRegAliasIterator AI(Src, TRI, tru 113 isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, const TargetRegisterInfo *TRI) argument [all...] |
H A D | InterferenceCache.h | 25 const TargetRegisterInfo *TRI; member in class:llvm::InterferenceCache 112 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI); 115 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI); 120 const TargetRegisterInfo *TRI, 150 InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {}
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H A D | RegisterScavenging.cpp | 34 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 40 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 74 TRI = TM.getRegisterInfo(); 77 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && 87 NumPhysRegs = TRI->getNumRegs(); 94 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF); 107 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 220 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 237 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && 262 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI [all...] |
H A D | AggressiveAntiDepBreaker.cpp | 122 TRI(MF.getTarget().getRegisterInfo()), 128 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); 138 dbgs() << " " << TRI->getName(r)); 148 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); 159 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 172 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 175 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 203 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 212 dbgs() << " " << TRI->getName(Reg) << "=g" << 250 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSel [all...] |
H A D | CriticalAntiDepBreaker.cpp | 34 TRI(MF.getTarget().getRegisterInfo()), 36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)), 37 KillIndices(TRI->getNumRegs(), 0), 38 DefIndices(TRI->getNumRegs(), 0), 39 KeepRegs(TRI->getNumRegs(), false) {} 46 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { 65 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 78 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 80 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 100 for (unsigned Reg = 0; Reg != TRI [all...] |
/freebsd-10.3-release/contrib/llvm/lib/Target/R600/ |
H A D | SIFixSGPRCopies.cpp | 86 const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI, 90 const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI, 94 bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI, 116 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { argument 123 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 133 const SIRegisterInfo *TRI, 143 RC = TRI->getSubRegClass(RC, SubReg); 148 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, 159 const SIRegisterInfo *TRI, 132 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument 158 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument 176 isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI) const argument 196 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( local [all...] |
H A D | R600ExpandSpecialInstrs.cpp | 61 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 169 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 177 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); 190 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 193 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; 196 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); 220 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && 221 (TRI.getEncodingValue(Src1) & 0xff) < 127) 222 assert(TRI [all...] |
/freebsd-10.3-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.h | 90 const TargetRegisterInfo *TRI) const { 91 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); 98 const TargetRegisterInfo *TRI) const { 99 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); 106 const TargetRegisterInfo *TRI, 113 const TargetRegisterInfo *TRI,
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H A D | Mips16FrameLowering.h | 37 const TargetRegisterInfo *TRI) const; 42 const TargetRegisterInfo *TRI) const;
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H A D | MipsFrameLowering.cpp | 104 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); local 113 for (const uint16_t *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) { 114 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
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/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.h | 41 const TargetRegisterInfo *TRI) const; 45 const TargetRegisterInfo *TRI) const;
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H A D | Thumb1InstrInfo.h | 50 const TargetRegisterInfo *TRI) const; 56 const TargetRegisterInfo *TRI) const;
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H A D | Thumb2InstrInfo.h | 52 const TargetRegisterInfo *TRI) const; 58 const TargetRegisterInfo *TRI) const;
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/freebsd-10.3-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.h | 37 const TargetRegisterInfo *TRI) const; 47 const TargetRegisterInfo *TRI) const;
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H A D | HexagonFrameLowering.cpp | 212 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument 213 MCSuperRegIterator SRI(Reg, TRI); 226 const TargetRegisterInfo *TRI) const { 247 unsigned SuperReg = uniqueSuperReg(Reg, TRI); 252 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); 253 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); 260 CSI[i+1].getFrameIdx(), SuperRegClass, TRI); 266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 268 TRI); 280 const TargetRegisterInfo *TRI) cons [all...] |
/freebsd-10.3-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.h | 45 const TargetRegisterInfo *TRI) const; 49 const TargetRegisterInfo *TRI) const;
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/freebsd-10.3-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.h | 36 const TargetRegisterInfo *TRI) const; 40 const TargetRegisterInfo *TRI) const;
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/freebsd-10.3-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.h | 68 const TargetRegisterInfo *TRI) const; 72 const TargetRegisterInfo *TRI) const; 92 const TargetRegisterInfo *TRI,
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H A D | AArch64AsmPrinter.cpp | 34 const TargetRegisterInfo *TRI, 39 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { 41 O << RegType << TRI->getEncodingValue(MO.getReg()); 53 const TargetRegisterInfo *TRI, 67 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { 148 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 161 if (!printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI, 168 if (!printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI, 191 if (!printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI, 228 if (printModifiedFPRAsmOperand(MO, TRI, ' 33 printModifiedFPRAsmOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI, char RegType, raw_ostream &O) argument 52 printModifiedGPRAsmOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI, const TargetRegisterClass &RegClass, raw_ostream &O) argument [all...] |