Searched refs:RegVT (Results 1 - 12 of 12) sorted by relevance

/freebsd-10.3-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp457 EVT RegVT = VA.getLocVT(); local
458 switch (RegVT.getSimpleVT().SimpleTy) {
463 << RegVT.getSimpleVT().SimpleTy << "\n";
470 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
476 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
479 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
/freebsd-10.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h280 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
286 MVT RegVT; member in struct:llvm::SelectionDAGBuilder::BitTestBlock
H A DSelectionDAGBuilder.cpp1861 B.RegVT = VT.getSimpleVT();
1862 B.Reg = FuncInfo.CreateReg(B.RegVT);
1896 MVT VT = BB.RegVT;
6116 MVT RegVT = *PhysReg.second->vt_begin();
6117 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
6119 RegVT, OpInfo.CallOperand);
6120 OpInfo.ConstraintVT = RegVT;
6121 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6126 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6128 RegVT, OpInf
[all...]
H A DLegalizeVectorOps.cpp541 EVT RegVT = Value.getValueType(); local
542 EVT RegSclVT = RegVT.getScalarType();
H A DLegalizeDAG.cpp333 MVT RegVT = local
338 unsigned RegBytes = RegVT.getSizeInBits() / 8;
342 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
355 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
377 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
459 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); local
461 unsigned RegBytes = RegVT.getSizeInBits() / 8;
465 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
475 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
494 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chai
[all...]
H A DLegalizeIntegerTypes.cpp717 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); local
719 // The argument is passed as NumRegs registers of type RegVT.
723 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
739 DAG.getConstant(i * RegVT.getSizeInBits(),
/freebsd-10.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp868 EVT RegVT = VA.getLocVT(); local
869 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
870 RegVT == MVT::i32 || RegVT == MVT::f32) {
874 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
875 } else if (RegVT == MVT::i64) {
879 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
/freebsd-10.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2602 MVT RegVT = VA.getLocVT(); local
2604 const TargetRegisterClass *RC = getRegClassFor(RegVT);
2609 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2621 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
2628 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2629 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2630 (RegVT == MVT::f64 && ValVT == MVT::i64))
2632 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2635 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3260 MVT RegVT local
3293 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); local
3320 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); local
[all...]
/freebsd-10.3-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1136 EVT RegVT = VA.getLocVT(); local
1137 switch (RegVT.getSimpleVT().SimpleTy) {
1142 << RegVT.getSimpleVT().SimpleTy << "\n";
1149 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
/freebsd-10.3-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2207 EVT RegVT = VA.getLocVT(); local
2209 if (RegVT == MVT::i32)
2211 else if (Is64Bit && RegVT == MVT::i64)
2213 else if (RegVT == MVT::f32)
2215 else if (RegVT == MVT::f64)
2217 else if (RegVT.is512BitVector())
2219 else if (RegVT.is256BitVector())
2221 else if (RegVT.is128BitVector())
2223 else if (RegVT == MVT::x86mmx)
2225 else if (RegVT
2593 EVT RegVT = VA.getLocVT(); local
18077 EVT RegVT = Ld->getValueType(0); local
[all...]
/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp2069 EVT RegVT = VA.getLocVT(); local
2083 if (RegVT == MVT::v2f64) {
2992 EVT RegVT = VA.getLocVT(); local
3023 if (RegVT == MVT::f32)
3025 else if (RegVT == MVT::f64)
3027 else if (RegVT == MVT::v2f64)
3029 else if (RegVT == MVT::i32)
3034 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3038 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3051 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValu
[all...]
/freebsd-10.3-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1169 MVT RegVT = VA.getLocVT(); local
1170 const TargetRegisterClass *RC = getRegClassFor(RegVT);
1173 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);

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