/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb2RegisterInfo.h | 37 unsigned PredReg = 0,
|
H A D | Thumb1RegisterInfo.h | 43 unsigned PredReg = 0,
|
H A D | Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
|
H A D | Thumb2RegisterInfo.cpp | 39 ARMCC::CondCodes Pred, unsigned PredReg, 34 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
|
H A D | ARMLoadStoreOptimizer.cpp | 99 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, 113 unsigned PredReg, 119 ARMCC::CondCodes Pred, unsigned PredReg, 290 unsigned PredReg, unsigned Scratch, DebugLoc dl, 344 .addImm(Pred).addReg(PredReg).addReg(0); 355 .addImm(Pred).addReg(PredReg); 431 ARMCC::CondCodes Pred, unsigned PredReg, 483 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) 525 ARMCC::CondCodes Pred, unsigned PredReg, 579 Base, false, Opcode, Pred, PredReg, Scratc 286 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument 425 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument 523 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument 609 isMatchingDecrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument 642 isMatchingIncrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument 798 unsigned PredReg = 0; local 951 unsigned PredReg = 0; local 1152 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1209 unsigned PredReg = 0; local 1328 unsigned PredReg = 0; local 1655 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument 1821 unsigned BaseReg = 0, PredReg = 0; local 1918 unsigned PredReg = 0; local [all...] |
H A D | Thumb2InstrInfo.cpp | 62 unsigned PredReg = 0; local 63 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); 110 unsigned PredReg = 0; local 111 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 216 ARMCC::CondCodes Pred, unsigned PredReg, 221 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 238 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 245 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 254 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 260 .addImm((unsigned)Pred).addReg(PredReg) 213 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
H A D | Thumb2ITBlockPass.cpp | 170 unsigned PredReg = 0; local 171 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
|
H A D | ARMBaseRegisterInfo.cpp | 396 unsigned PredReg, unsigned MIFlags) const { 407 .addImm(0).addImm(Pred).addReg(PredReg) 750 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); local 758 Offset, Pred, PredReg, TII); 762 Offset, Pred, PredReg, TII); 391 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
|
H A D | ARMBaseInstrInfo.h | 379 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 400 ARMCC::CondCodes Pred, unsigned PredReg, 406 ARMCC::CondCodes Pred, unsigned PredReg,
|
H A D | MLxExpansionPass.cpp | 284 unsigned PredReg = MI->getOperand(++NextOp).getReg(); local 297 MIB.addImm(Pred).addReg(PredReg); 309 MIB.addImm(Pred).addReg(PredReg);
|
H A D | ARMBaseRegisterInfo.h | 171 unsigned PredReg = 0,
|
H A D | Thumb2SizeReduction.cpp | 583 unsigned PredReg = 0; local 584 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 687 unsigned PredReg = 0; local 688 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 784 unsigned PredReg = 0; local 785 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
H A D | ARMFrameLowering.cpp | 113 unsigned PredReg = 0) { 116 Pred, PredReg, TII, MIFlags); 119 Pred, PredReg, TII, MIFlags); 127 unsigned PredReg = 0) { 129 MIFlags, Pred, PredReg); 1431 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1432 unsigned PredReg = Old->getOperand(2).getReg(); local 1434 Pred, PredReg); 1436 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1437 unsigned PredReg local [all...] |
H A D | Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg, 80 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) 373 unsigned PredReg; 374 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { 64 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
|
H A D | ARMExpandPseudoInsts.cpp | 617 unsigned PredReg = 0; local 618 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); 641 LO16.addImm(Pred).addReg(PredReg).addReg(0); 642 HI16.addImm(Pred).addReg(PredReg).addReg(0); 678 LO16.addImm(Pred).addReg(PredReg); 679 HI16.addImm(Pred).addReg(PredReg);
|
H A D | ARMConstantIslandPass.cpp | 1350 unsigned PredReg = 0; local 1351 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); 1796 unsigned PredReg = 0; local 1797 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); 1815 Pred = getInstrPredicate(CmpMI, PredReg);
|
H A D | ARMBaseInstrInfo.cpp | 1619 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { argument 1622 PredReg = 0; 1626 PredReg = MI->getOperand(PIdx+1).getReg(); 1649 unsigned PredReg = 0; local 1650 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1652 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1827 ARMCC::CondCodes Pred, unsigned PredReg, 1832 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1854 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1824 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
|
H A D | ARMISelDAGToDAG.cpp | 2504 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2505 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; 2767 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2768 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2787 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2788 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2806 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2807 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
|
/freebsd-10.3-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg(); local 501 MachineInstr *CondI = MRI->getVRegDef(PredReg);
|