/freebsd-10.3-release/contrib/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument 265 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument 280 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 358 unsigned Op1, Op2; local 359 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 364 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 371 unsigned Op1, Op2; local 372 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 377 DecodeGRRegsRegisterClass(Inst, Op2, Addres 384 unsigned Op1, Op2; local 397 unsigned Op1, Op2; local 411 unsigned Op1, Op2; local 424 unsigned Op1, Op2; local 437 unsigned Op1, Op2; local 522 unsigned Op1, Op2; local 536 unsigned Op1, Op2; local 550 unsigned Op1, Op2, Op3; local 563 unsigned Op1, Op2, Op3; local 576 unsigned Op1, Op2, Op3; local 589 unsigned Op1, Op2, Op3; local 602 unsigned Op1, Op2, Op3; local 616 unsigned Op1, Op2, Op3; local 631 unsigned Op1, Op2, Op3; local 645 unsigned Op1, Op2, Op3; local 659 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 693 unsigned Op1, Op2, Op3, Op4, Op5; local 713 unsigned Op1, Op2, Op3; local 732 unsigned Op1, Op2, Op3; local [all...] |
/freebsd-10.3-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 106 SDValue Op1, SDValue Op2, 147 SDValue Op1, SDValue Op2, 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 104 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 145 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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/freebsd-10.3-release/sys/contrib/dev/acpica/compiler/ |
H A D | asltree.c | 1171 * Op2 - Second peer 1182 ACPI_PARSE_OBJECT *Op2) 1190 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode) : NULL); 1193 if ((!Op1) && (!Op2)) 1201 if (!Op2) 1208 return (Op2); 1211 if (Op1 == Op2) 1221 Op1->Asl.Parent = Op2 1180 TrLinkPeerNode( ACPI_PARSE_OBJECT *Op1, ACPI_PARSE_OBJECT *Op2) argument 1317 TrLinkChildNode( ACPI_PARSE_OBJECT *Op1, ACPI_PARSE_OBJECT *Op2) argument [all...] |
H A D | aslcompiler.h | 750 ACPI_PARSE_OBJECT *Op2); 755 ACPI_PARSE_OBJECT *Op2);
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/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
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H A D | ARMFastISel.cpp | 118 unsigned Op2, bool Op2IsKill); 375 unsigned Op2, bool Op2IsKill) { 383 Op2 = constrainOperandRegClass(II, Op1, 3); 389 .addReg(Op2, Op2IsKill * RegState::Kill)); 394 .addReg(Op2, Op2IsKill * RegState::Kill)); 1900 unsigned Op2 = getRegForValue(I->getOperand(1)); local 1901 if (Op2 == 0) return false; 1906 .addReg(Op1).addReg(Op2)); 371 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
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/freebsd-10.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 587 SDValue Op2 = Op.getOperand(2); local 590 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 623 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 630 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); 631 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 662 SDValue Op2 = Op.getOperand(2); local 690 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); [all...] |
H A D | SelectionDAG.cpp | 271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 273 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 277 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 295 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 297 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 302 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 759 SDValue Op1, SDValue Op2, 764 SDValue Ops[] = { Op1, Op2 }; 5098 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { argument 5102 if (Op1 == N->getOperand(0) && Op2 758 FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, void *&InsertPos) argument 5127 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) argument 5133 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument 5140 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument 5210 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) argument 5218 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5268 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5276 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5285 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 5432 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument 5440 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5469 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5477 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5494 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument 5503 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument [all...] |
H A D | SelectionDAGBuilder.cpp | 2733 SDValue Op2 = getValue(I.getOperand(1)); 2735 Op2.getValueType(), Op2)); 2744 SDValue Op2 = getValue(I.getOperand(1)); 2746 Op1.getValueType(), Op1, Op2)); 2751 SDValue Op2 = getValue(I.getOperand(1)); 2753 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType()); 2756 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2758 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2763 Op2 [all...] |
H A D | LegalizeIntegerTypes.cpp | 181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 185 Op2, N->getMemOperand(), N->getOrdering(), 194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 198 Op2, Op3, N->getMemOperand(), N->getOrdering(), 863 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 865 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), 1419 unsigned Op1, Op2; local 1422 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1424 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1433 SDValue Sh1 = DAG.getNode(Op2, d [all...] |
/freebsd-10.3-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 789 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 795 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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H A D | SelectionDAG.h | 576 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument 582 Ops.push_back(Op2); 831 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); 832 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 834 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 836 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 848 SDValue Op1, SDValue Op2); 850 SDValue Op1, SDValue Op2, SDValue Op3); 864 EVT VT2, SDValue Op1, SDValue Op2); 866 EVT VT2, SDValue Op1, SDValue Op2, SDValu [all...] |
H A D | FastISel.h | 278 unsigned Op2, bool Op2IsKill);
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H A D | SelectionDAGNodes.h | 746 const SDValue &Op2) { 752 Ops[2].setInitial(Op2); 760 const SDValue &Op2, const SDValue &Op3) { 766 Ops[2].setInitial(Op2);
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/freebsd-10.3-release/contrib/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 152 ICToken Op2 = OperandStack.pop_back_val(); local 159 Val = Op1.second + Op2.second; 163 Val = Op1.second - Op2.second; 167 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 169 Val = Op1.second * Op2.second; 173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 175 assert (Op2.second != 0 && "Division by zero!"); 176 Val = Op1.second / Op2.second; 2129 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 2130 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) { 2142 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 2156 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 2169 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); local 2199 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); local [all...] |
/freebsd-10.3-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | LoopRerollPass.cpp | 958 Value *Op2 = J2->getOperand(j); local 964 if (Instruction *Op2I = dyn_cast<Instruction>(Op2)) 968 DenseMap<Value *, Value *>::iterator BMI = BaseMap.find(Op2); 970 Op2 = BMI->second; 972 (Instruction*) Op2) != Roots[i].end()) 973 Op2 = IV; 975 if (J1->getOperand(Swapped ? unsigned(!j) : j) != Op2) { 982 J1->getOperand(!j) == Op2) {
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/freebsd-10.3-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 299 MachineOperand Op2 = MI->getOperand(S2); local 300 ChangeOpInto(MI->getOperand(S1), Op2);
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H A D | HexagonHardwareLoops.cpp | 524 const MachineOperand &Op2 = CondI->getOperand(2); local 528 if (Op2.isImm() || Op1.getReg() == IVReg) 529 EndValue = &Op2;
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/freebsd-10.3-release/contrib/llvm/lib/Analysis/ |
H A D | ConstantFolding.cpp | 1541 if (ConstantFP *Op2 = dyn_cast<ConstantFP>(Operands[1])) { 1542 if (Op2->getType() != Op1->getType()) 1547 Op2V = Op2->getValueAPF().convertToFloat(); 1549 Op2V = Op2->getValueAPF().convertToDouble(); 1552 APFloat APF = Op2->getValueAPF(); 1586 if (ConstantInt *Op2 = dyn_cast<ConstantInt>(Operands[1])) { 1600 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); 1603 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); 1606 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); 1609 Res = Op1->getValue().usub_ov(Op2 [all...] |
/freebsd-10.3-release/contrib/llvm/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 589 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 594 Ops.push_back(Op2); 607 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 612 Ops.push_back(Op2);
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/freebsd-10.3-release/contrib/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 786 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local 791 Ops[4].getAsInteger(10, Op2); 792 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 818 uint32_t Op2 = Bits & 0x7; local 831 + "_c" + utostr(CRm) + "_" + utostr(Op2);
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/freebsd-10.3-release/contrib/llvm/include/llvm/Support/ |
H A D | PatternMatch.h | 1101 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument 1102 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2)); 1107 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument 1108 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
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/freebsd-10.3-release/contrib/llvm/lib/AsmParser/ |
H A D | LLParser.cpp | 3422 BasicBlock *Op1, *Op2; 3436 ParseTypeAndBasicBlock(Op2, Loc2, PFS)) 3439 Inst = BranchInst::Create(Op1, Op2, Op0); 3757 Value *Op0, *Op1, *Op2; 3762 ParseTypeAndValue(Op2, PFS)) 3765 if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2)) 3768 Inst = SelectInst::Create(Op0, Op1, Op2); 3811 Value *Op0, *Op1, *Op2; 3816 ParseTypeAndValue(Op2, PFS)) 3819 if (!InsertElementInst::isValidOperands(Op0, Op1, Op2)) [all...] |
/freebsd-10.3-release/contrib/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCompares.cpp | 2510 Value *Op1 = 0, *Op2 = 0; local 2514 Op2 = ConstantExpr::getICmp(I.getPredicate(), C, RHSC); 2522 if ((Op1 && Op2) || (LHSI->hasOneUse() && (Op1 || Op2))) { 2526 if (!Op2) 2527 Op2 = Builder->CreateICmp(I.getPredicate(), LHSI->getOperand(2), 2529 return SelectInst::Create(LHSI->getOperand(0), Op1, Op2); 3320 Value *Op1 = 0, *Op2 = 0; local 3326 Op2 = Builder->CreateFCmp(I.getPredicate(), 3330 Op2 [all...] |
/freebsd-10.3-release/contrib/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.cpp | 603 unsigned Op1, Op2, NewDstIdx; local 604 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 607 NewDstIdx = Op2; 608 else if (Op2 == UseOpIdx)
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