/freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
H A D | SITypeRewriter.cpp | 14 /// v16i8 => i128 15 /// - v16i8 is used for constant memory resource descriptors. This type is 17 /// in the backend, because we want the legalizer to expand all v16i8 38 Type *v16i8; member in class:__anon2606::SITypeRewriter 59 v16i8 = VectorType::get(Type::getInt8Ty(M.getContext()), 16); 87 if (ElemTy == v16i8) { 110 if (Arg->getType() == v16i8) {
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H A D | SIISelLowering.cpp | 122 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
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/freebsd-10.2-release/contrib/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 227 { ISD::SHL, MVT::v16i8, 1 }, // psllw. 232 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. 237 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 259 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence. 264 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized. 269 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized. 280 { ISD::SDIV, MVT::v16i8, 16*20 }, 284 { ISD::UDIV, MVT::v16i8, 16*20 }, 372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 [all...] |
H A D | X86ISelLowering.cpp | 935 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 940 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 946 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 960 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 971 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 996 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 997 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custo [all...] |
H A D | X86FastISel.cpp | 283 case MVT::v16i8:
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/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 74 v16i8 = 23, // 16 x i8 enumerator in enum:llvm::MVT::SimpleValueType 216 return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 || 277 case v16i8: 321 case v16i8: 408 case v16i8: 517 if (NumElements == 16) return MVT::v16i8;
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 230 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 231 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 234 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 460 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 } 514 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, 515 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, 516 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, 517 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
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H A D | ARMISelDAGToDAG.cpp | 1805 case MVT::v16i8: OpcodeIndex = 0; break; 1941 case MVT::v16i8: OpcodeIndex = 0; break; 2270 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0); 2761 case MVT::v16i8: Opc = ARM::VZIPq8; break; 2781 case MVT::v16i8: Opc = ARM::VUZPq8; break; 2800 case MVT::v16i8: Opc = ARM::VTRNq8; break; 3311 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
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H A D | ARMISelLowering.cpp | 468 addQRTypeForNEON(MVT::v16i8); 572 // v8i8/v16i8 vcnt instruction. 991 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 3988 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count 4005 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; 4324 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 5178 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT))); 5288 assert((VT == MVT::v8i16 || VT == MVT::v16i8) && 5289 "Expect an v8i16/v16i8 type"); 5291 // For a v16i8 typ [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 68 DecodePALIGNRMask(MVT::v16i8, 152 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask); 225 DecodeUNPCKLMask(MVT::v16i8, ShuffleMask);
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/freebsd-10.2-release/contrib/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 141 case MVT::v16i8: return "v16i8"; 209 case MVT::v16i8: return VectorType::get(Type::getInt8Ty(Context), 16);
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/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 371 // We promote all shuffles to v16i8. 373 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 442 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); 474 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 757 assert(N->getValueType(0) == MVT::v16i8 && 795 assert(N->getValueType(0) == MVT::v16i8 && 831 assert(N->getValueType(0) == MVT::v16i8 && 843 // splatted with a v16i8 mas [all...] |
H A D | PPCISelDAGToDAG.cpp | 631 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32). 638 if (VecVT == MVT::v16i8) 652 if (VecVT == MVT::v16i8) 665 if (VecVT == MVT::v16i8) 694 // types (v16i8, v8i16, v4i32, and v4f32). 697 case MVT::v16i8: 1325 VT = MVT::v16i8;
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/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 205 else if (RC->hasType(MVT::v16i8)) 246 else if (RC->hasType(MVT::v16i8))
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H A D | MipsSEISelDAGToDAG.cpp | 801 ViaVecTy = MVT::v16i8;
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H A D | MipsSEISelLowering.cpp | 88 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); 2225 ViaVecTy = MVT::v16i8;
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H A D | MipsISelLowering.cpp | 2950 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 2983 if (VT == MVT::v16i8)
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/freebsd-10.2-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 82 case MVT::v16i8: return "MVT::v16i8";
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/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 70 addRegisterClass(MVT::v16i8, &AArch64::FPR128RegClass); 286 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 302 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 314 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Legal); 325 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 2916 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3415 EVT CanonicalVT = VT.is128BitVector() ? MVT::v16i8 : MVT::v8i8;
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