Searched refs:ed_asic_inb (Results 1 - 7 of 7) sorted by relevance

/freebsd-10.2-release/sys/dev/ed/
H A Dif_ed_wd80x3.c119 sum += ed_asic_inb(sc, ED_WD_PROM + i);
127 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
128 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
138 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
143 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
174 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
204 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
205 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
225 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
251 && ((ed_asic_inb(s
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H A Dif_ed_hpp.c145 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
146 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
147 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
148 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
158 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
160 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
210 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
H A Dif_ed_pccard.c680 sum += ed_asic_inb(sc, i);
687 device_printf(dev, "CIR is %d\n", ed_asic_inb(sc, 0xa));
689 sc->enaddr[i] = ed_asic_inb(sc, 0x04 + i);
691 id = ed_asic_inb(sc, 0xf);
761 val = ed_asic_inb(sc, ED_DL100XX_MIIBUS);
778 ed_asic_outb(sc, ED_NOVELL_RESET, ed_asic_inb(sc, ED_NOVELL_RESET));
832 if (ed_asic_inb(sc, ED_AX88X90_TEST) != 0)
979 val = ed_asic_inb(sc, ED_AX88X90_MIIBUS);
1052 val = ed_asic_inb(sc, ED_TC5299J_MIIBUS);
H A Dif_ed_3c503.c89 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
135 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
H A Dif_ed_novell.c82 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
H A Dif_ed_cbus.c692 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
695 (void) ed_asic_inb(sc, 0x08);
707 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
782 sc->enaddr[n] = ed_asic_inb(sc, ED_NC5098_ENADDR + n);
1399 val |= (ed_asic_inb(sc, ED_SB98_EEP) & ED_SB98_EEP_SDA);
H A Dif_edvar.h160 #define ed_asic_inb(sc, port) \ macro

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