| /freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 261 MBB.addLiveIn(SuperReg);
269 MBB.addLiveIn(Reg);
315 MBB.addLiveIn(SuperReg);
322 MBB.addLiveIn(Reg);
|
| H A D | HexagonCFGOptimizer.cpp | 223 LayoutSucc->addLiveIn(NewLiveIn[i]);
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 127 MBB.addLiveIn(XCore::LR);
150 MBB.addLiveIn(XCore::LR);
166 MBB.addLiveIn(XCore::R10);
286 MBB.addLiveIn(it->getReg());
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430FrameLowering.cpp | 76 I->addLiveIn(MSP430::FPW);
198 MBB.addLiveIn(Reg);
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 145 MF.getRegInfo().addLiveIn(Mips::T9_64);
146 MBB.addLiveIn(Mips::T9_64);
173 MF.getRegInfo().addLiveIn(Mips::T9);
174 MBB.addLiveIn(Mips::T9);
208 MF.getRegInfo().addLiveIn(Mips::V0);
209 MBB.addLiveIn(Mips::V0);
|
| H A D | Mips16FrameLowering.cpp | 121 EntryBlock->addLiveIn(Reg);
|
| H A D | MipsSEFrameLowering.cpp | 357 MBB.addLiveIn(ehDataReg(I));
461 EntryBlock->addLiveIn(Reg);
|
| H A D | MipsDelaySlotFiller.cpp | 287 MBB.addLiveIn(R);
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.cpp | 119 MBB.addLiveIn(GPR64);
203 MBB.addLiveIn(Reg);
383 I->addLiveIn(SystemZ::R11D);
|
| /freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 392 EntryMBB->addLiveIn(LiveIns[i].first);
396 EntryMBB->addLiveIn(LiveIns[i].first);
|
| H A D | VirtRegMap.cpp | 258 LiveIn[i]->addLiveIn(PhysReg);
|
| H A D | MachineBasicBlock.cpp | 346 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { function in class:MachineBasicBlock
373 addLiveIn(PhysReg);
812 NMBB->addLiveIn(*I);
|
| H A D | MachineFunction.cpp | 421 /// addLiveIn - Add the specified physical register as a live-in value and
423 unsigned MachineFunction::addLiveIn(unsigned PReg, function in class:MachineFunction
432 MRI.addLiveIn(PReg, VReg);
|
| H A D | BranchFolding.cpp | 387 NewMBB->addLiveIn(i);
1725 TBB->addLiveIn(Def);
1726 FBB->addLiveIn(Def);
|
| H A D | MachineCSE.cpp | 574 MBB->addLiveIn(LiveIn);
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 540 I->addLiveIn(FramePtr);
988 MBB.addLiveIn(Reg);
1008 MBB.addLiveIn(Reg);
1183 allocMBB->addLiveIn(*i);
1184 checkMBB->addLiveIn(*i);
1188 allocMBB->addLiveIn(X86::R10);
1425 stackCheckMBB->addLiveIn(*I);
1426 incStackMBB->addLiveIn(*I);
|
| /freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineBasicBlock.h | 295 /// addLiveIn - Add the specified register as a live in. Note that it
297 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } function in class:llvm::MachineBasicBlock
302 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
|
| H A D | MachineFunction.h | 307 /// addLiveIn - Add the specified physical register as a live-in value and
309 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
|
| H A D | MachineRegisterInfo.h | 519 /// addLiveIn - Add the specified register as a live-in. Note that it
521 void addLiveIn(unsigned Reg, unsigned vreg = 0) { function in class:llvm::MachineRegisterInfo
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 232 MBB->addLiveIn(reg - SP::I0 + SP::O0);
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 619 MBB.addLiveIn(Reg);
814 MBB.addLiveIn(SupReg);
832 MBB.addLiveIn(SupReg);
844 MBB.addLiveIn(SupReg);
853 MBB.addLiveIn(NextReg);
|
| H A D | Thumb1FrameLowering.cpp | 357 MBB.addLiveIn(Reg);
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 257 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
296 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
303 Reg = MF.addLiveIn(Reg, RC);
316 Reg = MF.addLiveIn(Reg, RC);
|
| /freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 2041 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2133 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2152 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2328 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2367 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2390 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2417 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2419 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2437 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2492 unsigned VReg = MF.addLiveIn(GP
[all...] |
| /freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 419 MBB.addLiveIn(Reg);
|