Searched refs:Writes (Results 1 - 7 of 7) sorted by relevance
| /freebsd-10.2-release/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.h | 109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
126 /// that mapped the itinerary class to the variant Writes or Reads.
132 IdxVec Writes; member in struct:llvm::CodeGenSchedClass
148 return ItinClassDef == IC && Writes == W && Reads == R;
338 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
350 const IdxVec &Writes,
396 void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
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| H A D | CodeGenSchedule.cpp | 192 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
300 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
390 IdxVec &Writes, IdxVec &Reads) const {
394 findRWs(WriteDefs, Writes, false);
517 IdxVec Writes, Reads;
519 findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
524 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
560 if (!SC.Writes.empty()) {
563 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes
[all...] |
| H A D | SubtargetEmitter.cpp | 882 IdxVec Writes = SCI->Writes; local
897 Writes.clear();
900 Writes, Reads);
903 if (Writes.empty()) {
911 Writes, Reads);
915 if (Writes.empty()) {
925 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
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| /freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBundle.h | 158 /// Writes - One of the operands writes the virtual register.
159 bool Writes; member in struct:llvm::MachineOperandIteratorBase::VirtRegInfo
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| /freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 273 RI.Writes = true;
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| H A D | InlineSpiller.cpp | 1237 if (RI.Writes) {
1280 if (RI.Writes)
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| H A D | RegisterCoalescer.cpp | 958 bool Reads, Writes; local
959 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
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