Searched refs:UL (Results 1 - 25 of 387) sorted by relevance

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/freebsd-10.2-release/sys/sparc64/include/
H A Dlsu.h34 #define LSU_IC (1UL << 0)
35 #define LSU_DC (1UL << 1)
36 #define LSU_IM (1UL << 2)
37 #define LSU_DM (1UL << 3)
42 #define LSU_FM_MASK (((1UL << LSU_FM_BITS) - 1) << LSU_FM_SHIFT)
46 #define LSU_VM_MASK (((1UL << LSU_VM_BITS) - 1) << LSU_VM_SHIFT)
50 #define LSU_PM_MASK (((1UL << LSU_PM_BITS) - 1) << LSU_PM_SHIFT)
52 #define LSU_VW (1UL << 21)
53 #define LSU_VR (1UL << 22)
54 #define LSU_PW (1UL << 2
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H A Ddcr.h35 #define DCR_MS (1UL << 0)
36 #define DCR_IFPOE (1UL << 1)
37 #define DCR_SI (1UL << 3)
38 #define DCR_RPE (1UL << 4)
39 #define DCR_BPE (1UL << 5)
44 (((1UL << DCR_OBSDATA_CT_BITS) - 1) << DCR_OBSDATA_SHIFT)
47 #define DCR_IPE (1UL << 2)
51 (((1UL << DCR_OBSDATA_CTP_BITS) - 1) << DCR_OBSDATA_SHIFT)
53 #define DCR_DPE (1UL << 12)
59 (((1UL << DCR_BPM_BIT
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H A Dccr.h32 #define ICC_MASK ((1UL << ICC_BITS) - 1)
33 #define ICC_C (1UL << 0)
34 #define ICC_V (1UL << 1)
35 #define ICC_Z (1UL << 2)
36 #define ICC_N (1UL << 3)
40 #define XCC_MASK (((1UL << XCC_BITS) - 1) << XCC_SHIFT)
41 #define XCC_C (1UL << 4)
42 #define XCC_V (1UL << 5)
43 #define XCC_Z (1UL << 6)
44 #define XCC_N (1UL <<
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H A Dmcntl.h35 #define MCNTL_JPS1_TSBP (1UL << 8)
40 (((1UL << MCNTL_RMD_BITS) - 1) << MCNTL_RMD_SHIFT)
41 #define MCNTL_RMD_FULL (0UL << MCNTL_RMD_SHIFT)
42 #define MCNTL_RMD_1024 (2UL << MCNTL_RMD_SHIFT)
43 #define MCNTL_RMD_512 (3UL << MCNTL_RMD_SHIFT)
45 #define MCNTL_FW_FDTLB (1UL << 14)
46 #define MCNTL_FW_FITLB (1UL << 15)
47 #define MCNTL_NC_CACHE (1UL << 16)
50 #define MCNTL_MPG_SDTLB (1UL << 6)
51 #define MCNTL_MPG_SITLB (1UL <<
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H A Drunq.h32 #define RQB_LEN (1UL) /* Number of priority status words. */
33 #define RQB_L2BPW (6UL) /* Log2(sizeof(rqb_word_t) * NBBY)). */
34 #define RQB_BPW (1UL<<RQB_L2BPW) /* Bits in an rqb_word_t. */
36 #define RQB_BIT(pri) (1UL << ((pri) & (RQB_BPW - 1)))
53 for (bit = 1; (mask & 1UL) == 0; bit++)
54 mask >>= 1UL;
H A Dtte.h64 #define TD_SIZE_MASK ((1UL << TD_SIZE_BITS) - 1)
65 #define TD_SOFT2_MASK ((1UL << TD_SOFT2_BITS) - 1)
66 #define TD_RSVD2_MASK ((1UL << TD_RSVD2_BITS) - 1)
67 #define TD_SIZE2_MASK ((1UL << TD_SIZE2_BITS) - 1)
68 #define TD_DIAG_SF_MASK ((1UL << TD_DIAG_SF_BITS) - 1)
69 #define TD_RSVD_CH_MASK ((1UL << TD_RSVD_CH_BITS) - 1)
70 #define TD_RSVD_OC_MASK ((1UL << TD_RSVD_OC_BITS) - 1)
71 #define TD_RSVD_PT_MASK ((1UL << TD_RSVD_PT_BITS) - 1)
72 #define TD_RSVD_VE_MASK ((1UL << TD_RSVD_VE_BITS) - 1)
73 #define TD_PA_CH_MASK ((1UL << TD_PA_CH_BIT
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/freebsd-10.2-release/contrib/ntp/tests/libntp/
H A Dnumtoa.c24 const u_int32 input = htonl(3221225472UL + 512UL + 1UL); // 192.0.2.1
32 const u_int32 hostOrder = 255UL*256UL*256UL*256UL + 255UL*256UL*256UL
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H A Dprettydate.c24 const u_int32 HALF = 2147483648UL;
26 l_fp e_time = {{3485080800UL}, HALF}; /* 2010-06-09 14:00:00.5 */
H A Duglydate.c23 const u_int32 HALF = 2147483648UL;
25 l_fp e_time = {{3485080800UL}, HALF}; /* 2010-06-09 14:00:00.5 */
H A Dcalyearstart.c28 const u_int32 input = 3486372600UL; // 2010-06-24 12:50:00.
29 const u_int32 expected = 3471292800UL; // 2010-01-01 00:00:00
36 const u_int32 input = 3549528000UL; // 2012-06-24 12:00:00
37 const u_int32 expected = 3534364800UL; // 2012-01-01 00:00:00
44 const u_int32 input = 19904UL; // 2036-02-07 12:00:00
45 const u_int32 expected = 4291747200UL; // 2036-01-01 00:00:00
/freebsd-10.2-release/sys/arm/ti/
H A Dti_i2c.h43 #define I2C_IE_XDR (1UL << 14) /* Transmit draining interrupt */
44 #define I2C_IE_RDR (1UL << 13) /* Receive draining interrupt */
45 #define I2C_IE_AAS (1UL << 9) /* Addressed as Slave interrupt */
46 #define I2C_IE_BF (1UL << 8) /* Bus Free interrupt */
47 #define I2C_IE_AERR (1UL << 7) /* Access Error interrupt */
48 #define I2C_IE_STC (1UL << 6) /* Start Condition interrupt */
49 #define I2C_IE_GC (1UL << 5) /* General Call interrupt */
50 #define I2C_IE_XRDY (1UL << 4) /* Transmit Data Ready interrupt */
51 #define I2C_IE_RRDY (1UL << 3) /* Receive Data Ready interrupt */
52 #define I2C_IE_ARDY (1UL <<
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H A Dti_mmchs.h76 #define MMCHS_STAT_BADA (1UL << 29)
77 #define MMCHS_STAT_CERR (1UL << 28)
78 #define MMCHS_STAT_ACE (1UL << 24)
79 #define MMCHS_STAT_DEB (1UL << 22)
80 #define MMCHS_STAT_DCRC (1UL << 21)
81 #define MMCHS_STAT_DTO (1UL << 20)
82 #define MMCHS_STAT_CIE (1UL << 19)
83 #define MMCHS_STAT_CEB (1UL << 18)
84 #define MMCHS_STAT_CCRC (1UL << 17)
85 #define MMCHS_STAT_CTO (1UL << 1
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H A Dti_sdma.h64 #define TI_SDMA_STATUS_DROP (1UL << 1)
65 #define TI_SDMA_STATUS_HALF (1UL << 2)
66 #define TI_SDMA_STATUS_FRAME (1UL << 3)
67 #define TI_SDMA_STATUS_LAST (1UL << 4)
68 #define TI_SDMA_STATUS_BLOCK (1UL << 5)
69 #define TI_SDMA_STATUS_SYNC (1UL << 6)
70 #define TI_SDMA_STATUS_PKT (1UL << 7)
71 #define TI_SDMA_STATUS_TRANS_ERR (1UL << 8)
72 #define TI_SDMA_STATUS_SECURE_ERR (1UL << 9)
73 #define TI_SDMA_STATUS_SUPERVISOR_ERR (1UL << 1
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/freebsd-10.2-release/sys/arm/at91/
H A Dat91_pmcreg.h69 #define PMC_SCER_PCK (1UL << 0) /* PCK: Processor Clock Enable */
70 #define PMC_SCER_UDP (1UL << 1) /* UDP: USB Device Port Clock Enable */
71 #define PMC_SCER_MCKUDP (1UL << 2) /* MCKUDP: Master disable susp/res */
72 #define PMC_SCER_UHP (1UL << 4) /* UHP: USB Host Port Clock Enable */
73 #define PMC_SCER_PCK0 (1UL << 8) /* PCK0: Programmable Clock out en */
74 #define PMC_SCER_PCK1 (1UL << 9) /* PCK1: Programmable Clock out en */
75 #define PMC_SCER_PCK2 (1UL << 10) /* PCK2: Programmable Clock out en */
76 #define PMC_SCER_PCK3 (1UL << 11) /* PCK3: Programmable Clock out en */
77 #define PMC_SCER_UHP_SAM9 (1UL << 6) /* UHP: USB Host Port Clock Enable */
78 #define PMC_SCER_UDP_SAM9 (1UL <<
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H A Dat91_usartreg.h32 #define USART_CR_RSTRX (1UL << 2) /* Reset Receiver */
33 #define USART_CR_RSTTX (1UL << 3) /* Reset Transmitter */
34 #define USART_CR_RXEN (1UL << 4) /* Receiver Enable */
35 #define USART_CR_RXDIS (1UL << 5) /* Receiver Disable */
36 #define USART_CR_TXEN (1UL << 6) /* Transmitter Enable */
37 #define USART_CR_TXDIS (1UL << 7) /* Transmitter Disable */
38 #define USART_CR_RSTSTA (1UL << 8) /* Reset Status Bits */
39 #define USART_CR_STTBRK (1UL << 9) /* Start Break */
40 #define USART_CR_STPBRK (1UL << 10) /* Stop Break */
41 #define USART_CR_STTTO (1UL << 1
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H A Dat91_pdcreg.h43 #define PDC_PTCR_RXTEN (1UL << 0) /* RXTEN: Receiver Transfer Enable */
44 #define PDC_PTCR_RXTDIS (1UL << 1) /* RXTDIS: Receiver Transfer Disable */
45 #define PDC_PTCR_TXTEN (1UL << 8) /* TXTEN: Transmitter Transfer En */
46 #define PDC_PTCR_TXTDIS (1UL << 9) /* TXTDIS: Transmitter Transmit Dis */
/freebsd-10.2-release/sys/dev/isci/scil/
H A Dscu_viit_data.h71 #define SCU_VIIT_ENTRY_ID_SHIFT (30UL)
74 #define SCU_VIIT_ENTRY_FUNCTION_SHIFT (20UL)
77 #define SCU_VIIT_ENTRY_IPPTMODE_SHIFT (12UL)
80 #define SCU_VIIT_ENTRY_LPVIE_SHIFT (8UL)
83 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0UL)
85 #define SCU_VIIT_ENTRY_ID_INVALID (0UL << SCU_VIIT_ENTRY_ID_SHIFT)
86 #define SCU_VIIT_ENTRY_ID_VIIT (1UL << SCU_VIIT_ENTRY_ID_SHIFT)
87 #define SCU_VIIT_ENTRY_ID_IIT (2UL << SCU_VIIT_ENTRY_ID_SHIFT)
88 #define SCU_VIIT_ENTRY_ID_VIRT_EXP (3UL << SCU_VIIT_ENTRY_ID_SHIFT)
145 #define SCU_IIT_ENTRY_ID_SHIFT (30UL)
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H A Dscu_registers.h91 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0UL)
93 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT (12UL)
95 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT (16UL)
97 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT (18UL)
105 #define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT (31UL)
107 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT (1UL)
109 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0UL)
121 #define SMU_INTERRUPT_MASK_COMPLETION_SHIFT (31UL)
123 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT (1UL)
125 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT (0UL)
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/freebsd-10.2-release/sys/arm/ti/usb/
H A Domap_usb.h140 #define TLL_SYSCONFIG_CACTIVITY (1UL << 8)
141 #define TLL_SYSCONFIG_SIDLE_SMART_IDLE (2UL << 3)
142 #define TLL_SYSCONFIG_SIDLE_NO_IDLE (1UL << 3)
143 #define TLL_SYSCONFIG_SIDLE_FORCED_IDLE (0UL << 3)
144 #define TLL_SYSCONFIG_ENAWAKEUP (1UL << 2)
145 #define TLL_SYSCONFIG_SOFTRESET (1UL << 1)
146 #define TLL_SYSCONFIG_AUTOIDLE (1UL << 0)
148 #define TLL_SYSSTATUS_RESETDONE (1UL << 0)
150 #define TLL_SHARED_CONF_USB_90D_DDR_EN (1UL << 6)
151 #define TLL_SHARED_CONF_USB_180D_SDR_EN (1UL <<
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/freebsd-10.2-release/sys/powerpc/include/
H A Drunq.h33 #define RQB_LEN (1UL) /* Number of priority status words. */
34 #define RQB_L2BPW (6UL) /* Log2(sizeof(rqb_word_t) * NBBY)). */
39 #define RQB_BPW (1UL<<RQB_L2BPW) /* Bits in an rqb_word_t. */
41 #define RQB_BIT(pri) (1UL << ((pri) & (RQB_BPW - 1)))
/freebsd-10.2-release/contrib/ntp/tests/sandbox/
H A Duglydate.c25 const u_int32 HALF = 2147483648UL;
27 l_fp e_time = {{3485080800UL}, HALF}; // 2010-06-09 14:00:00.5
/freebsd-10.2-release/sys/dev/pccbb/
H A Dpccbbreg.h203 #define CBB_STATE_CSTCHG (1UL << 0) /* Card Status Change */
204 #define CBB_STATE_CD1_CHANGE (1UL << 1) /* Card Detect 1 */
205 #define CBB_STATE_CD2_CHANGE (1UL << 2) /* Card Detect 2 */
206 #define CBB_STATE_CD (3UL << 1) /* Card Detect all */
207 #define CBB_STATE_POWER_CYCLE (1UL << 3) /* Power Cycle */
208 #define CBB_STATE_R2_CARD (1UL << 4) /* 16-bit Card */
209 #define CBB_STATE_CB_CARD (1UL << 5) /* Cardbus Card */
210 #define CBB_STATE_IREQ (1UL << 6) /* Ready */
211 #define CBB_STATE_NOT_A_CARD (1UL << 7) /* Unrecognized Card */
212 #define CBB_STATE_DATA_LOST (1UL <<
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/freebsd-10.2-release/sys/xen/interface/
H A Dnmi.h38 #define XEN_NMIREASON_io_error (1UL << _XEN_NMIREASON_io_error)
41 #define XEN_NMIREASON_parity_error (1UL << _XEN_NMIREASON_parity_error)
44 #define XEN_NMIREASON_unknown (1UL << _XEN_NMIREASON_unknown)
/freebsd-10.2-release/sys/sparc64/pci/
H A Dpsychoreg.h276 #define UEAFSR_BLK (1UL << 23) /* Error caused by block transaction */
277 #define UEAFSR_P_DTE (1UL << 56) /* Pri. DVMA translation error */
278 #define UEAFSR_S_DTE (1UL << 57) /* Sec. DVMA translation error */
279 #define UEAFSR_S_DWR (1UL << 58) /* Sec. error during DVMA write */
280 #define UEAFSR_S_DRD (1UL << 59) /* Sec. error during DVMA read */
281 #define UEAFSR_S_PIO (1UL << 60) /* Sec. error during PIO access */
282 #define UEAFSR_P_DWR (1UL << 61) /* Pri. error during DVMA write */
283 #define UEAFSR_P_DRD (1UL << 62) /* Pri. error during DVMA read */
284 #define UEAFSR_P_PIO (1UL << 63) /* Pri. error during PIO access */
287 #define CEAFSR_BLK (1UL << 2
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/freebsd-10.2-release/sys/arm/include/
H A Dvmparam.h45 #define MAXTSIZ (64UL*1024*1024) /* max text size */
48 #define DFLDSIZ (128UL*1024*1024) /* initial data size limit */
51 #define MAXDSIZ (512UL*1024*1024) /* max data size */
54 #define DFLSSIZ (2UL*1024*1024) /* initial stack size limit */
57 #define MAXSSIZ (8UL*1024*1024) /* max stack size */
60 #define SGROWSIZ (128UL*1024) /* amount to grow stack */

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