/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 239 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 242 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 244 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 246 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 248 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 250 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 252 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 254 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 256 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 258 { ISD::UINT_TO_FP, MV [all...] |
H A D | ARMISelLowering.cpp | 111 setOperationAction(ISD::UINT_TO_FP, VT, Custom); 116 setOperationAction(ISD::UINT_TO_FP, VT, Expand); 558 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 563 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 862 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 3683 case ISD::UINT_TO_FP: 3685 Opc = ISD::UINT_TO_FP; 3706 case ISD::UINT_TO_FP: 6123 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 9664 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 369 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 370 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 371 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 378 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 379 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, 380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 427 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 428 { ISD::UINT_TO_FP, MV [all...] |
H A D | X86ISelLowering.cpp | 313 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 315 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 316 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 317 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 320 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 321 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 325 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 328 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 857 setOperationAction(ISD::UINT_TO_FP, VT, Expand); 1025 setOperationAction(ISD::UINT_TO_FP, MV [all...] |
/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 368 UINT_TO_FP, enumerator in enum:llvm::ISD::NodeType
|
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 258 case ISD::UINT_TO_FP: 272 case ISD::UINT_TO_FP: 295 else if (Node->getOpcode() == ISD::UINT_TO_FP) 366 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : 713 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
|
H A D | SelectionDAGDumper.cpp | 223 case ISD::UINT_TO_FP: return "uint_to_fp";
|
H A D | LegalizeVectorTypes.cpp | 93 case ISD::UINT_TO_FP: 553 case ISD::UINT_TO_FP: 1158 case ISD::UINT_TO_FP: 1555 case ISD::UINT_TO_FP: 2353 case ISD::UINT_TO_FP:
|
H A D | LegalizeDAG.cpp | 1181 case ISD::UINT_TO_FP: 2388 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2393 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2448 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2471 // If the target supports UINT_TO_FP of this type, use it. 2472 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2473 OpToUse = ISD::UINT_TO_FP; 2984 case ISD::UINT_TO_FP: 3874 if (Node->getOpcode() == ISD::UINT_TO_FP || 3924 case ISD::UINT_TO_FP [all...] |
H A D | LegalizeFloatTypes.cpp | 100 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break; 840 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break; 1228 llvm_unreachable("Unsupported UINT_TO_FP!");
|
H A D | DAGCombiner.cpp | 1175 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 6546 // but UINT_TO_FP is legal on this target, try to convert. 6548 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6549 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6551 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); 6600 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); 6602 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6604 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 9626 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { 9649 assert((Opcode == ISD::UINT_TO_FP || Opcod [all...] |
H A D | LegalizeIntegerTypes.cpp | 801 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 2490 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 2826 llvm_unreachable("Unsupported UINT_TO_FP!"); 2865 "Don't know how to expand this UINT_TO_FP!");
|
H A D | SelectionDAG.cpp | 2524 case ISD::UINT_TO_FP:
|
H A D | SelectionDAGBuilder.cpp | 2912 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
|
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 141 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 171 setOperationAction(ISD::UINT_TO_FP, VT, Expand); 273 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 721 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo); 724 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
|
H A D | R600ISelLowering.cpp | 1507 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { 1508 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
|
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1157 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); 1162 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); 1167 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); 1172 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); 1177 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal); 1192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
|
/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 217 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 317 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 341 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 453 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); 4862 "UINT_TO_FP is supported only with FPCVT"); 4867 (Op.getOpcode() == ISD::UINT_TO_FP ? 4869 (Op.getOpcode() == ISD::UINT_TO_FP ? 4956 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ? 5798 case ISD::UINT_TO_FP [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 260 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 261 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 262 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); 2873 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
|
/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1426 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 1428 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 2806 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, 3208 case ISD::UINT_TO_FP:
|
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1284 case UIToFP: return ISD::UINT_TO_FP;
|
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 196 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); 1708 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
|
H A D | MipsISelLowering.cpp | 292 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 293 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
|
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 178 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); 179 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
|