Searched refs:ShiftOp (Results 1 - 5 of 5) sorted by relevance
/freebsd-10.2-release/contrib/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 524 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); local 525 if (ShiftOp && !ShiftOp->isShift()) 526 ShiftOp = 0; 528 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) { 542 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1)); 547 Value *X = ShiftOp->getOperand(0); 552 if (I.getOpcode() == ShiftOp->getOpcode()) { 569 ShiftOp [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 709 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); 710 bool isASR = (ShiftOp & (1 << 5)) != 0; 711 unsigned Amt = ShiftOp & 0x1f;
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 1461 unsigned ShiftOp = MI.getOperand(3).getImm(); 1462 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
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/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 2114 SDValue ShiftOp = N->getOperand(1); local 2119 if (ShiftOp.getValueType() != ShiftTy) 2120 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); 2122 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
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H A D | SelectionDAGBuilder.cpp | 1897 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), 1907 ShiftOp, 1914 ShiftOp, 1920 DAG.getConstant(1, VT), ShiftOp);
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