Searched refs:SelectVLD (Results 1 - 2 of 2) sorted by relevance
/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 120 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, 670 SDNode *AArch64DAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, function in class:AArch64DAGToDAGISel 1179 return SelectVLD(Node, true, 1, Opcodes); 1188 return SelectVLD(Node, true, 2, Opcodes); 1197 return SelectVLD(Node, true, 3, Opcodes); 1206 return SelectVLD(Node, true, 4, Opcodes); 1215 return SelectVLD(Node, true, 2, Opcodes); 1224 return SelectVLD(Node, true, 3, Opcodes); 1233 return SelectVLD(Node, true, 4, Opcodes); 1427 return SelectVLD(Nod [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 212 /// SelectVLD - Select NEON load intrinsics. NumVecs should be 216 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, 1778 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, function in class:ARMDAGToDAGISel 2876 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0); 2887 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0); 2901 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1); 2915 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1); 3130 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0); 3138 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0); 3152 return SelectVLD( [all...] |
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