Searched refs:SchedWrites (Results 1 - 2 of 2) sorted by relevance

/freebsd-10.2-release/contrib/llvm/utils/TableGen/
H A DCodeGenSchedule.h40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
234 std::vector<CodeGenSchedRW> SchedWrites; member in class:llvm::CodeGenSchedModels
288 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
289 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
290 return SchedWrites[Idx];
H A DCodeGenSchedule.cpp109 // defined, and populate SchedReads and SchedWrites vectors. Implicit
212 SchedWrites.resize(1);
288 SchedWrites.push_back(CodeGenSchedRW(SchedWrites.size(), *SWI));
296 for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(),
297 WE = SchedWrites.end(); WI != WE; ++WI) {
314 for (unsigned WIdx = 0, WEnd = SchedWrites.size(); WIdx != WEnd; ++WIdx) {
316 SchedWrites[WIdx].dump();
349 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
469 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
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