/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.h | 110 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { argument 112 if (!isAllocated(Regs[i])) 137 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { argument 138 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 143 unsigned Reg = Regs[FirstUnalloc]; 149 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, argument 151 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 156 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
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/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | RegisterScavenging.h | 180 void setUsed(BitVector &Regs) { argument 181 RegsAvailable.reset(Regs); 183 void setUnused(BitVector &Regs) { argument 184 RegsAvailable |= Regs;
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H A D | CallingConvLower.h | 281 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const { argument 283 if (!isAllocated(Regs[i])) 308 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { argument 309 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 314 unsigned Reg = Regs[FirstUnalloc]; 320 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, argument 322 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 327 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
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H A D | RegisterPressure.h | 305 void addLiveRegs(ArrayRef<unsigned> Regs); 429 void increaseRegPressure(ArrayRef<unsigned> Regs); 430 void decreaseRegPressure(ArrayRef<unsigned> Regs);
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/freebsd-10.2-release/contrib/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor); 59 const std::vector<CodeGenRegister*> &Regs, 171 const CodeGenRegister::Set &Regs = RC.getMembers(); local 172 if (Regs.empty()) 177 OS << " {" << (*Regs.begin())->getWeight(RegBank) 315 const std::vector<CodeGenRegister*> &Regs, 323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 324 Record *Reg = Regs[i]->TheDef; 342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 390 for (unsigned i = 0, e = Regs 314 EmitRegMappingTables(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument 440 EmitRegMapping(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument 708 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local 1214 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local 1306 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); local [all...] |
H A D | CodeGenRegisters.cpp | 159 RegUnitIterator(const CodeGenRegister::Set &Regs): argument 160 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { 944 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); local 945 std::sort(Regs.begin(), Regs.end(), LessRecordRegister()); 946 Registers.reserve(Regs.size()); 948 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 949 getReg(Regs[i]); 1235 CodeGenRegister::Set Regs; member in struct:__anon3861::UberRegSet 1266 const CodeGenRegister::Set &Regs = RegClass->getMembers(); local 1974 computeCoveredRegisters(ArrayRef<Record*> Regs) argument [all...] |
H A D | CodeGenTarget.cpp | 222 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); local 223 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 224 if (I == Regs.end())
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H A D | CodeGenRegisters.h | 670 // Compute the set of registers completely covered by the registers in Regs. 671 // The returned BitVector will have a bit set for each register in Regs, 673 // registers in Regs. 677 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
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H A D | AsmMatcherEmitter.cpp | 2189 const std::vector<CodeGenRegister*> &Regs = 2191 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 2192 const CodeGenRegister *Reg = Regs[i];
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/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 51 const unsigned *Regs) { 53 RegNo = Regs[RegNo]; 189 const unsigned *Regs) { 193 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 199 const unsigned *Regs) { 203 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 209 const unsigned *Regs) { 214 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 216 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); 221 const unsigned *Regs) { 50 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs) argument [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, 318 RegisterGroup Group, const unsigned *Regs, RegisterKind Kind); 322 const unsigned *Regs, RegisterKind RegKind); 326 const unsigned *Regs, RegisterKind RegKind, 480 // Parse a register of group Group. If Regs is nonnull, use it to map 485 const unsigned *Regs, bool IsAddress) { 490 if (Regs && Regs[Reg.Num] == 0) 494 if (Regs) 495 Reg.Num = Regs[Re 484 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) argument 501 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) argument 520 parseAddress(unsigned &Base, const MCExpr *&Disp, unsigned &Index, const MCExpr *&Length, const unsigned *Regs, RegisterKind RegKind) argument 570 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, const unsigned *Regs, RegisterKind RegKind, MemoryKind MemKind) argument [all...] |
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
H A D | ExecutionDepsFix.cpp | 645 SmallVector<LiveReg, 4> Regs; local 656 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end(); 660 Regs.insert(i, LR); 664 Regs.push_back(LR); 670 while (!Regs.empty()) { 672 dv = Regs.pop_back_val().Value; 679 DomainValue *Latest = Regs.pop_back_val().Value;
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H A D | AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
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H A D | AggressiveAntiDepBreaker.cpp | 70 std::vector<unsigned> &Regs, 75 Regs.push_back(Reg); 537 std::vector<unsigned> Regs; 538 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); 539 assert(Regs.size() > 0 && "Empty register group!"); 540 if (Regs.size() == 0) 550 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 551 unsigned Reg = Regs[i]; 570 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 571 unsigned Reg = Regs[ 68 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) argument [all...] |
H A D | RegisterPressure.cpp | 422 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { argument 423 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 424 if (LiveRegs.insert(Regs[i])) 425 increaseRegPressure(Regs[i]);
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 595 SmallVector<std::pair<unsigned,bool>, 4> Regs; local 627 Regs.push_back(std::make_pair(Reg, isKill)); 630 if (Regs.empty()) 632 if (Regs.size() > 1 || StrOpc== 0) { 636 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 637 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 638 } else if (Regs.size() == 1) { 641 .addReg(Regs[0].first, getKillRegState(Regs[ 667 SmallVector<unsigned, 4> Regs; local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 101 ArrayRef<std::pair<unsigned, bool> > Regs, 283 /// registers in Regs as the register operands that would be loaded / stored. 291 ArrayRef<std::pair<unsigned, bool> > Regs, 294 unsigned NumRegs = Regs.size(); 324 NewBase = Regs[NumRegs-1].first; 357 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 358 | getKillRegState(Regs[i].second)); 453 SmallVector<std::pair<unsigned, bool>, 8> Regs; local 461 Regs.push_back(std::make_pair(Reg, isKill)); 483 Pred, PredReg, Scratch, dl, Regs, ImpDef 286 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument [all...] |
H A D | Thumb2SizeReduction.cpp | 214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) 215 if (*Regs == ARM::CPSR)
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/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 432 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { argument 439 return createTuple(Regs, RegClassIDs, SubRegs); 442 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { argument 449 return createTuple(Regs, RegClassIDs, SubRegs); 452 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, argument 457 if (Regs.size() == 1) 458 return Regs[0]; 460 assert(Regs.size() >= 2 && Regs.size() <= 4); 462 SDLoc DL(Regs[ [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 826 SmallPtrSet<const SCEV *, 16> &Regs, 839 SmallPtrSet<const SCEV *, 16> &Regs, 843 SmallPtrSet<const SCEV *, 16> &Regs, 853 SmallPtrSet<const SCEV *, 16> &Regs, 875 if (!Regs.count(AR->getOperand(1))) { 876 RateRegister(AR->getOperand(1), Regs, L, SE, DT); 901 SmallPtrSet<const SCEV *, 16> &Regs, 909 if (Regs.insert(Reg)) { 910 RateRegister(Reg, Regs, L, SE, DT); 918 SmallPtrSet<const SCEV *, 16> &Regs, 852 RateRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument 900 RatePrimaryRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument 916 RateFormula(const TargetTransformInfo &TTI, const Formula &F, SmallPtrSet<const SCEV *, 16> &Regs, const DenseSet<const SCEV *> &VisitedRegs, const Loop *L, const SmallVectorImpl<int64_t> &Offsets, ScalarEvolution &SE, DominatorTree &DT, const LSRUse &LU, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument 1192 SmallPtrSet<const SCEV *, 4> Regs; member in class:__anon2792::LSRUse 3775 SmallPtrSet<const SCEV *, 16> Regs; local [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 312 SmallVector<SDValue, 4> Regs; local 313 Regs.push_back(Val); 317 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT)); 323 Regs.push_back(DAG.getUNDEF(VT)); 326 Regs.data(), Regs.size()));
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/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 603 /// Regs - This list holds the registers assigned to the values. 607 SmallVector<unsigned, 4> Regs; member in struct:__anon2333::RegsForValue 613 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 624 Regs.push_back(Reg + i); 644 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 701 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 703 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 712 if (!TargetRegisterInfo::isVirtualRegister(Regs[Par [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 2357 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs, argument 2359 assert (Regs.size() > 0 && "RegList contains no registers?"); 2362 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2365 contains(Regs.front().second)) 2369 array_pod_sort(Regs.begin(), Regs.end()); 2373 I = Regs.begin(), E = Regs.end(); I != E; ++I)
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