Searched refs:RS480_GART_CACHE_CNTRL (Results 1 - 6 of 6) sorted by relevance
/freebsd-10.2-release/sys/dev/drm2/radeon/ |
H A D | rs400.c | 67 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 69 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 75 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 336 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
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H A D | radeon_cp.c | 957 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 963 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 967 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 973 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
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H A D | r500_reg.h | 149 #define RS480_GART_CACHE_CNTRL 0x2e macro
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H A D | radeon_drv.h | 586 #define RS480_GART_CACHE_CNTRL 0x2e macro
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/freebsd-10.2-release/sys/dev/drm/ |
H A D | radeon_cp.c | 898 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 904 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 908 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 914 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
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H A D | radeon_drv.h | 664 #define RS480_GART_CACHE_CNTRL 0x2e macro
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