/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 152 EVT NewVT = N->getValueType(0).getVectorElementType(); local 154 NewVT, N->getOperand(0)); 168 EVT NewVT = N->getValueType(0).getVectorElementType(); local 170 return DAG.getConvertRndSat(NewVT, SDLoc(N), 171 Op0, DAG.getValueType(NewVT), 185 EVT NewVT = N->getValueType(0).getVectorElementType(); local 188 NewVT, Op, N->getOperand(1)); 1006 EVT NewVT = Inputs[0].getValueType(); local 1007 unsigned NewElts = NewVT.getVectorNumElements(); 1064 EVT EltVT = NewVT 2414 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); local 2628 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); local 2836 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); local [all...] |
H A D | LegalizeTypesGeneric.cpp | 210 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); local 223 NewVT, 2*OldElts), 230 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 234 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 368 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); local 390 NewVT, NewElts.size()),
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H A D | DAGCombiner.cpp | 2172 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 2173 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2174 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2175 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2176 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2177 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2208 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 2209 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2210 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2211 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N 2290 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 2320 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 8328 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); local [all...] |
H A D | SelectionDAG.cpp | 3646 EVT NewVT = VT; local 3651 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; 3652 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) && 3653 TLI.isSafeMemOpType(NewVT.getSimpleVT())) 3655 else if (NewVT == MVT::i64 && 3659 NewVT = MVT::f64; 3666 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); 3667 if (NewVT == MVT::i8) 3669 } while (!TLI.isSafeMemOpType(NewVT [all...] |
H A D | LegalizeDAG.cpp | 3110 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, 3112 assert(NewVT.bitsEq(VT)); 3115 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); 3116 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); 3119 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements(); 3135 VT = NewVT;
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/freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 865 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); local 866 if (!TLI->isTypeLegal(NewVT)) 867 NewVT = EltTy; 868 IntermediateVT = NewVT; 870 unsigned NewVTSize = NewVT.getSizeInBits(); 876 MVT DestVT = TLI->getRegisterType(NewVT); 878 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1158 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); local 1159 if (!isTypeLegal(NewVT)) 1160 NewVT [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCalls.cpp | 668 VectorType *NewVT = cast<VectorType>(II->getType()); local 669 unsigned NewWidth = NewVT->getElementType()->getIntegerBitWidth(); 682 ConstantInt::get(NewVT->getElementType(), CV0E * CV1E));
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/freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 1234 EVT NewVT = MVT::v4i32; local 1237 NewVT = VT; 1240 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements);
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/freebsd-10.2-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 6674 MVT NewVT; local 6678 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break; 6679 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break; 6680 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break; 6681 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break; 6682 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; 6683 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; 6701 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0)); 6702 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); 6703 return DAG.getVectorShuffle(NewVT, d 7241 MVT NewVT = NewOp.getSimpleValueType(); local 7250 MVT NewVT = NewOp.getSimpleValueType(); local 9841 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); local 12425 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); local 12981 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); local 13122 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); local [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 5599 EVT NewVT = getExtensionTo64Bits(OrigTy); 5601 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
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