Searched refs:NewMIs (Results 1 - 12 of 12) sorted by relevance

/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp567 SmallVectorImpl<MachineInstr*> &NewMIs,
575 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
581 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
586 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
591 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
596 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
633 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
636 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
644 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
663 SmallVector<MachineInstr*, 4> NewMIs; local
563 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument
692 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument
776 SmallVector<MachineInstr*, 4> NewMIs; local
[all...]
H A DPPCInstrInfo.h74 SmallVectorImpl<MachineInstr*> &NewMIs,
79 SmallVectorImpl<MachineInstr*> &NewMIs,
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp1200 SmallVector<MachineInstr *, 2> NewMIs; local
1203 NewMIs)) {
1207 assert(NewMIs.size() == 2 &&
1210 NewMIs[1]->addRegisterKilled(Reg, TRI);
1214 MBB->insert(mi, NewMIs[0]);
1215 MBB->insert(mi, NewMIs[1]);
1217 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1218 << "2addr: NEW INST: " << *NewMIs[1]); local
1221 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1222 unsigned NewSrcIdx = NewMIs[
[all...]
H A DMachineLICM.cpp1268 SmallVector<MachineInstr *, 2> NewMIs; local
1272 NewMIs);
1277 assert(NewMIs.size() == 2 &&
1281 MBB->insert(Pos, NewMIs[0]);
1282 MBB->insert(Pos, NewMIs[1]);
1285 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1286 NewMIs[0]->eraseFromParent();
1287 NewMIs[1]->eraseFromParent();
1292 UpdateRegPressure(NewMIs[
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.h263 SmallVectorImpl<MachineInstr*> &NewMIs) const;
276 SmallVectorImpl<MachineInstr*> &NewMIs) const;
309 SmallVectorImpl<MachineInstr*> &NewMIs) const;
H A DX86InstrInfo.cpp3238 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3249 NewMIs.push_back(MIB);
3272 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3282 NewMIs.push_back(MIB);
4513 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4560 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4564 MachineOperand &MO = NewMIs[0]->getOperand(i);
4621 NewMIs.push_back(DataMI);
4630 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h90 SmallVectorImpl<MachineInstr*> &NewMIs) const;
101 SmallVectorImpl<MachineInstr*> &NewMIs) const;
H A DHexagonInstrInfo.cpp510 SmallVectorImpl<MachineInstr*> &NewMIs) const
550 SmallVectorImpl<MachineInstr*> &NewMIs) const {
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.h116 SmallVectorImpl<MachineInstr *> &NewMIs) const;
H A DAMDGPUInstrInfo.cpp200 SmallVectorImpl<MachineInstr*> &NewMIs) const {
/freebsd-10.2-release/contrib/llvm/include/llvm/Target/
H A DTargetInstrInfo.h583 SmallVectorImpl<MachineInstr*> &NewMIs) const{
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp209 std::vector<MachineInstr*> NewMIs; local
219 NewMIs.push_back(MemMI);
220 NewMIs.push_back(UpdateMI);
232 NewMIs.push_back(UpdateMI);
233 NewMIs.push_back(MemMI);
252 MachineInstr *NewMI = NewMIs[j];
265 MFI->insert(MBBI, NewMIs[1]);
266 MFI->insert(MBBI, NewMIs[0]);
267 return NewMIs[0];

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