Searched refs:Lo (Results 1 - 25 of 50) sorted by relevance

12

/freebsd-10.2-release/sys/contrib/dev/acpica/components/utilities/
H A Dutmath.c65 UINT32 Lo; member in struct:uint64_struct
126 ACPI_DIV_64_BY_32 (Remainder32, DividendOvl.Part.Lo, Divisor,
127 Quotient.Part.Lo, Remainder32);
202 ACPI_DIV_64_BY_32 (0, Dividend.Part.Hi, Divisor.Part.Lo,
204 ACPI_DIV_64_BY_32 (Partial1, Dividend.Part.Lo, Divisor.Part.Lo,
205 Quotient.Part.Lo, Remainder.Part.Lo);
223 NormalizedDivisor.Part.Lo);
225 NormalizedDividend.Part.Lo);
[all...]
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.h164 SDValue JoinIntegers(SDValue Lo, SDValue Hi);
173 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
175 SDValue &Lo, SDValue &Hi);
298 /// of Op are exactly equal to the bits of Lo; the high bits exactly equal Hi.
300 /// method returns the two i32's, with Lo being equal to the lower 32 bits of
302 void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
303 void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
308 SDValue &Lo, SDValue &Hi);
309 void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
310 void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValu
699 GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument
728 GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument
[all...]
H A DLegalizeTypesGeneric.cpp14 // computation in two identical registers of a smaller type. The Lo/Hi part
30 // These routines assume that the Lo/Hi part is stored first in memory on
31 // little/big-endian machines, followed by the Hi/Lo part. This means that
32 // they cannot be used as is on vectors, for which Lo is always stored first.
34 SDValue &Lo, SDValue &Hi) {
36 GetExpandedOp(Op, Lo, Hi);
39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) { argument
53 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); local
54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
33 ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument
181 ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi) argument
188 ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
200 ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
240 ExpandRes_NormalLoad(SDNode *N, SDValue &Lo, SDValue &Hi) argument
284 ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) argument
380 SDValue Lo, Hi; local
398 SDValue Lo, Hi; local
422 SDValue Lo, Hi; local
471 SDValue Lo, Hi; local
500 SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument
506 SplitRes_SELECT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
528 SplitRes_SELECT_CC(SDNode *N, SDValue &Lo, SDValue &Hi) argument
541 SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) argument
[all...]
H A DLegalizeFloatTypes.cpp786 SDValue Lo, Hi; local
787 Lo = Hi = SDValue();
801 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
802 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
803 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
805 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
806 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
807 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
808 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
809 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, H
846 SetExpandedFloat(SDValue(N, ResNo), Lo, Hi); local
849 ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi) argument
863 ExpandFloatRes_FABS(SDNode *N, SDValue &Lo, SDValue &Hi) argument
877 ExpandFloatRes_FADD(SDNode *N, SDValue &Lo, SDValue &Hi) argument
887 ExpandFloatRes_FCEIL(SDNode *N, SDValue &Lo, SDValue &Hi) argument
897 ExpandFloatRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi) argument
909 ExpandFloatRes_FCOS(SDNode *N, SDValue &Lo, SDValue &Hi) argument
919 ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument
933 ExpandFloatRes_FEXP(SDNode *N, SDValue &Lo, SDValue &Hi) argument
943 ExpandFloatRes_FEXP2(SDNode *N, SDValue &Lo, SDValue &Hi) argument
953 ExpandFloatRes_FFLOOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument
963 ExpandFloatRes_FLOG(SDNode *N, SDValue &Lo, SDValue &Hi) argument
973 ExpandFloatRes_FLOG2(SDNode *N, SDValue &Lo, SDValue &Hi) argument
983 ExpandFloatRes_FLOG10(SDNode *N, SDValue &Lo, SDValue &Hi) argument
993 ExpandFloatRes_FMA(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1007 ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1021 ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1033 ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1041 ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1049 ExpandFloatRes_FPOW(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1059 ExpandFloatRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1069 ExpandFloatRes_FREM(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1079 ExpandFloatRes_FRINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1089 ExpandFloatRes_FROUND(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1101 ExpandFloatRes_FSIN(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1111 ExpandFloatRes_FSQRT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1121 ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1135 ExpandFloatRes_FTRUNC(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1145 ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1177 ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1357 SDValue Lo, Hi; local
1368 SDValue Lo, Hi; local
1481 SDValue Lo, Hi; local
[all...]
H A DLegalizeIntegerTypes.cpp237 SDValue Lo, Hi; local
238 GetSplitVector(N->getOperand(0), Lo, Hi);
239 Lo = BitConvertToInteger(Lo);
243 std::swap(Lo, Hi);
248 JoinIntegers(Lo, Hi));
904 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); local
906 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
911 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1077 SDValue Lo, H local
1115 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; local
1172 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); local
1271 ExpandShiftByConstant(SDNode *N, unsigned Amt, SDValue &Lo, SDValue &Hi) argument
1363 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1451 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1525 ExpandIntRes_ADDSUB(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1587 ExpandIntRes_ADDSUBC(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1613 ExpandIntRes_ADDSUBE(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1633 ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument
1639 ExpandIntRes_ANY_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1662 ExpandIntRes_AssertSext(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1683 ExpandIntRes_AssertZext(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1703 ExpandIntRes_BSWAP(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1711 ExpandIntRes_Constant(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1720 ExpandIntRes_CTLZ(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1739 ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1750 ExpandIntRes_CTTZ(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1769 ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1781 ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1793 ExpandIntRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi) argument
1910 ExpandIntRes_Logical(SDNode *N, SDValue &Lo, SDValue &Hi) argument
1920 ExpandIntRes_MUL(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2012 ExpandIntRes_SADDSUBO(SDNode *Node, SDValue &Lo, SDValue &Hi) argument
2054 ExpandIntRes_SDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2074 ExpandIntRes_Shift(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2175 ExpandIntRes_SIGN_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2207 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2233 ExpandIntRes_SREM(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2253 ExpandIntRes_TRUNCATE(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2264 ExpandIntRes_UADDSUBO(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2287 ExpandIntRes_XMULO(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2373 ExpandIntRes_UDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2393 ExpandIntRes_UREM(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2413 ExpandIntRes_ZERO_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2441 ExpandIntRes_ATOMIC_LOAD(SDNode *N, SDValue &Lo, SDValue &Hi) argument
2677 SDValue Lo, Hi; local
2686 SDValue Lo, Hi; local
2716 SDValue Lo, Hi; local
2829 SDValue Lo, Hi; local
[all...]
H A DLegalizeVectorTypes.cpp484 SDValue Lo, Hi; local
500 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
502 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
503 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
504 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
505 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
506 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
507 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
508 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
509 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, H
516 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); local
522 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); local
592 SetSplitVector(SDValue(N, ResNo), Lo, Hi); local
595 SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument
607 SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument
623 SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) argument
671 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); local
679 SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument
692 SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi) argument
713 SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument
729 SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument
766 SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi) argument
774 SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument
790 SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi) argument
841 SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument
850 SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi) argument
893 SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) argument
911 SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument
947 SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument
999 SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo, SDValue &Hi) argument
1195 SDValue Lo, Hi; local
1220 SDValue Lo, Hi; local
1238 SDValue Lo, Hi; local
1255 SDValue Lo, Hi; local
1318 SDValue Lo, Hi; local
1452 SDValue Lo, Hi; local
[all...]
H A DLegalizeTypes.cpp768 void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo, argument
774 Lo = Entry.first;
778 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo, argument
780 assert(Lo.getValueType() ==
782 Hi.getValueType() == Lo.getValueType() &&
784 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
785 AnalyzeNewValue(Lo);
791 Entry.first = Lo;
795 void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo, argument
801 Lo
805 SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi) argument
822 GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi) argument
832 SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi) argument
963 GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi) argument
988 JoinIntegers(SDValue Lo, SDValue Hi) argument
1074 SplitInteger(SDValue Op, EVT LoVT, EVT HiVT, SDValue &Lo, SDValue &Hi) argument
1088 SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi) argument
[all...]
H A DLegalizeVectorOps.cpp455 SDValue Lo, Hi, ShAmt; local
459 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
460 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
476 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
481 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
484 Lo = DAG.getZExtOrTrunc(Lo, d
[all...]
H A DLegalizeDAG.cpp406 SDValue Lo = Val; local
411 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
418 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
539 SDValue Lo, Hi; local
541 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
557 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
568 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
570 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
690 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); local
692 if (TLI.isBigEndian()) std::swap(Lo, H
[all...]
/freebsd-10.2-release/contrib/llvm/include/llvm/Support/
H A DSwapByteOrder.h34 uint16_t Lo = value >> 8;
35 return Hi | Lo;
66 uint32_t Lo = SwapByteOrder_32(uint32_t(value >> 32));
67 return (Hi << 32) | Lo;
H A DGCOV.h166 uint32_t Lo, Hi; local
167 if (!readInt(Lo) || !readInt(Hi)) return false;
168 Val = ((uint64_t)Hi << 32) | Lo;
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/
H A DMipsJITInfo.cpp179 int Lo = (int)(NewVal & 0xffff); local
182 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo;
219 int Lo = (int)(EmittedAddr & 0xffff); local
227 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
232 JCE.emitWordBE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
H A DMips16ISelDAGToDAG.cpp47 SDNode *Lo = 0, *Hi = 0; local
54 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
55 InFlag = SDValue(Lo, 1);
61 return std::make_pair(Lo, Hi);
213 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
H A DMipsISelLowering.h45 // No relation with Mips Lo register
46 Lo, enumerator in enum:llvm::MipsISD::NodeType
268 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, local
270 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
314 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); local
317 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
H A DMipsLongBranch.cpp273 int64_t Lo = SignExtend64<16>(Offset & 0xffff); local
305 .addReg(Mips::AT).addImm(Lo);
361 .addReg(Mips::AT_64).addImm(Lo);
H A DMipsISelLowering.cpp120 case MipsISD::Lo: return "MipsISD::Lo";
660 SDValue Lo = Add.getOperand(1);
662 if ((Lo.getOpcode() != MipsISD::Lo) ||
663 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
671 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1541 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); local
1543 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1564 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); local
1855 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); local
1886 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); local
2395 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, local
[all...]
/freebsd-10.2-release/contrib/llvm/include/llvm/IR/
H A DMDBuilder.h81 /// \brief Return metadata describing the range [Lo, Hi).
82 MDNode *createRange(const APInt &Lo, const APInt &Hi) { argument
83 assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths!");
85 if (Hi == Lo)
88 // Return the range [Lo, Hi).
89 Type *Ty = IntegerType::get(Context, Lo.getBitWidth());
90 Value *Range[2] = { ConstantInt::get(Ty, Lo), ConstantInt::get(Ty, Hi) };
/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp102 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
107 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
129 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
130 Addr.getOperand(1).getOpcode() == SPISD::Lo)
H A DSparcISelLowering.cpp814 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, local
822 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
829 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
845 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
1688 case SPISD::Lo: return "SPISD::Lo";
1797 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG)); local
1798 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1836 L44 = DAG.getNode(SPISD::Lo, D
1844 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, local
1927 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, local
1961 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, local
2705 SDValue Lo; local
[all...]
H A DSparcISelLowering.h36 Hi, Lo, // Hi/Lo operations, typically on a global address. enumerator in enum:llvm::SPISD::__anon2617
/freebsd-10.2-release/contrib/llvm/tools/clang/lib/CodeGen/
H A DTargetInfo.cpp1119 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
1125 /// \param Lo - The classification for the parts of the type
1131 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
1136 /// \param Lo - The classification for the parts of the type
1150 /// be passed in Memory then at least the classification of \arg Lo
1153 /// The \arg Lo class will be NoClass iff the argument is ignored.
1155 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
1157 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
1368 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, argument
1392 Lo
1441 classify(QualType Ty, uint64_t OffsetBase, Class &Lo, Class &Hi, bool isNamedArg) const argument
[all...]
/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/
H A DAsmPrinter.h353 /// EmitLabelDifference - Emit something like ".long Hi-Lo" where the size
354 /// in bytes of the directive is specified by Size and Hi/Lo specify the
356 void EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo,
359 /// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo"
360 /// where the size in bytes of the directive is specified by Size and Hi/Lo
363 const MCSymbol *Lo, unsigned Size) const;
/freebsd-10.2-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp548 SDValue Lo(Hi.getNode(), 1);
549 SDValue Ops[] = { Lo, Hi };
565 SDValue Lo(Hi.getNode(), 1);
566 SDValue Ops[] = { Lo, Hi };
662 SDValue Lo(Hi.getNode(), 1);
663 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
670 SDValue Lo(Hi.getNode(), 1);
671 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
681 SDValue Lo(Hi.getNode(), 1);
686 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, H
718 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), local
1490 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); local
[all...]
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/AsmPrinter/
H A DDIE.h330 DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo) argument
331 : DIEValue(isDelta), LabelHi(Hi), LabelLo(Lo) {}
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h43 Hi, Lo, // Hi/Lo operations, typically on a global address. enumerator in enum:llvm::HexagonISD::__anon2506

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