/freebsd-10.2-release/contrib/llvm/include/llvm/MC/ |
H A D | MCInstrItineraries.h | 195 /// index DefIdx can be bypassed when it's read by an instruction of 197 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, argument 201 if ((FirstDefIdx + DefIdx) >= LastDefIdx) 203 if (Forwardings[FirstDefIdx + DefIdx] == 0) 211 return Forwardings[FirstDefIdx + DefIdx] == 218 int getOperandLatency(unsigned DefClass, unsigned DefIdx, argument 223 int DefCycle = getOperandCycle(DefClass, DefIdx); 233 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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H A D | MCSubtargetInfo.h | 106 unsigned DefIdx) const { 107 assert(DefIdx < SC->NumWriteLatencyEntries && 108 "MachineModel does not specify a WriteResource for DefIdx"); 110 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
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/freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 129 unsigned DefIdx = 0; local 133 ++DefIdx; 135 return DefIdx; 189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); local 190 if (DefIdx < SCDesc->NumWriteLatencyEntries) { 193 STI->getWriteLatencyEntry(SCDesc, DefIdx); 209 // If DefIdx does not exist in the model (e.g. implicit defs), then return 217 ss << "DefIdx " << DefIdx << " exceeds machine model writes for " 241 for (unsigned DefIdx [all...] |
H A D | TargetInstrInfo.cpp | 617 SDNode *DefNode, unsigned DefIdx, 627 return ItinData->getOperandCycle(DefClass, DefIdx); 629 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 693 unsigned DefIdx) const { 698 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 706 const MachineInstr *DefMI, unsigned DefIdx, 710 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 739 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or 743 const MachineInstr *DefMI, unsigned DefIdx, 754 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseM 616 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument 705 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 742 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
H A D | PeepholeOptimizer.cpp | 364 unsigned SrcIdx, DefIdx; local 367 SrcIdx, DefIdx) != NULL; 386 /// and one register definition. Otherwise, \p DefIdx and \p SrcIdx 389 unsigned &DefIdx, unsigned &SrcIdx) { 395 DefIdx = 0; 397 assert(Copy.getOperand(DefIdx).isDef() && "Use comes before def!"); 411 DefIdx = OpIdx; 434 unsigned DefIdx, SrcIdx; local 435 if (!MI || !getCopyOrBitcastDefUseIdx(*MI, DefIdx, SrcIdx)) 438 const MachineOperand &MODef = MI->getOperand(DefIdx); 388 getCopyOrBitcastDefUseIdx(const MachineInstr &Copy, unsigned &DefIdx, unsigned &SrcIdx) argument [all...] |
H A D | LiveRangeEdit.cpp | 127 SlotIndex DefIdx; 129 DefIdx = LIS.getInstructionIndex(RM.OrigMI); 131 DefIdx = RM.ParentVNI->def; 132 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx); 141 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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H A D | LiveRangeCalc.cpp | 91 unsigned DefIdx; local 95 } else if (MI->isRegTiedToDefOperand(I.getOperandNo(), &DefIdx)) { 98 if (MI->getOperand(DefIdx).isEarlyClobber())
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H A D | MachineVerifier.cpp | 888 unsigned DefIdx; local 890 MI->isRegTiedToDefOperand(MONum, &DefIdx) && 891 Reg != MI->getOperand(DefIdx).getReg()) 1084 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); local 1085 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); 1088 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { 1090 if (VNI->def != DefIdx) { 1093 << DefIdx << " in " << LI << '\n'; 1097 *OS << DefIdx << " i [all...] |
H A D | MachineInstr.cpp | 703 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); local 704 if (DefIdx != -1) 705 tieOperands(DefIdx, OpNo); 966 unsigned DefIdx; local 967 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 968 OpIdx = DefIdx; 1100 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1112 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { argument 1113 MachineOperand &DefMO = getOperand(DefIdx); 1115 assert(DefMO.isDef() && "DefIdx mus [all...] |
H A D | RegisterCoalescer.cpp | 598 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); local 599 assert(DefIdx != -1); 601 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 701 SlotIndex DefIdx = UseIdx.getRegSlot(); local 702 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); 705 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); 706 assert(DVNI->def == DefIdx);
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H A D | InlineSpiller.cpp | 889 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM, local 891 (void)DefIdx; 892 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' 893 << *LIS.getInstructionFromIndex(DefIdx));
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H A D | RegAllocFast.cpp | 735 unsigned DefIdx = 0; local 736 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; 738 << DefIdx << ".\n"); local
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H A D | MachineLICM.cpp | 200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, 1010 unsigned DefIdx, unsigned Reg) const { 1029 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i)) 1009 HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg) const argument
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/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.h | 136 unsigned DefIdx; member in class:llvm::ScheduleDAGSDNodes::RegDefIter 154 return DefIdx-1;
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H A D | ScheduleDAGSDNodes.cpp | 553 DefIdx = 0; 559 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { 567 for (;DefIdx < NodeNumDefs; ++DefIdx) { 568 if (!Node->hasAnyUseOfValue(DefIdx)) 570 ValueType = Node->getSimpleValueType(DefIdx); 571 ++DefIdx; 633 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); 637 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
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H A D | InstrEmitter.cpp | 986 unsigned DefIdx = GroupIdx[DefGroup] + 1; 989 MIB->tieOperands(DefIdx + j, UseIdx + j);
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/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | TargetSchedule.h | 166 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
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H A D | MachineInstr.h | 833 /// tieOperands - Add a tie between the register operands at DefIdx and 839 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 223 const MachineInstr *DefMI, unsigned DefIdx, 227 SDNode *DefNode, unsigned DefIdx, 248 unsigned DefIdx, unsigned DefAlign) const; 252 unsigned DefIdx, unsigned DefAlign) const; 263 unsigned DefIdx, unsigned DefAlign, 278 const MachineInstr *DefMI, unsigned DefIdx, 281 const MachineInstr *DefMI, unsigned DefIdx) const;
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H A D | ARMBaseInstrInfo.cpp | 2980 unsigned DefIdx, unsigned DefAlign) const { 2981 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2984 return ItinData->getOperandCycle(DefClass, DefIdx); 3021 unsigned DefIdx, unsigned DefAlign) const { 3022 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3025 return ItinData->getOperandCycle(DefClass, DefIdx); 3124 unsigned DefIdx, unsigned DefAlign, 3130 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 3131 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 3140 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2977 getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument 3018 getLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument 3122 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument 3233 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument 3470 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3561 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument 3863 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
H A D | ARMISelDAGToDAG.cpp | 3460 unsigned DefIdx = 0; local 3464 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) 3465 IsTiedToChangedOp = OpChanged[DefIdx]; 3541 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
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/freebsd-10.2-release/contrib/llvm/lib/MC/MCDisassembler/ |
H A D | Disassembler.cpp | 230 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; 231 DefIdx != DefEnd; ++DefIdx) { 234 DefIdx);
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/freebsd-10.2-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 813 SDNode *DefNode, unsigned DefIdx, 825 const MachineInstr *DefMI, unsigned DefIdx, 832 const MachineInstr *DefMI, unsigned DefIdx, 867 const MachineInstr *DefMI, unsigned DefIdx, 876 const MachineInstr *DefMI, unsigned DefIdx) const; 865 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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/freebsd-10.2-release/contrib/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 389 const MachineInstr *DefMI, unsigned DefIdx,
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H A D | X86InstrInfo.cpp | 5306 const MachineInstr *DefMI, unsigned DefIdx, 5304 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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