Searched refs:CVMX_CIU_INTX_EN1 (Results 1 - 4 of 4) sorted by relevance

/freebsd-10.2-release/sys/mips/cavium/
H A Dciu.c373 mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
375 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), mask);
385 mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
387 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), mask);
400 mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(core*2));
405 cvmx_write_csr(CVMX_CIU_INTX_EN1(core*2), mask);
428 en1_mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
H A Docteon_machdep.c182 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
183 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
/freebsd-10.2-release/sys/contrib/octeon-sdk/
H A Dcvmx-interrupt.c438 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), cvmx_interrupt_ciu_en1_mirror);
478 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), cvmx_interrupt_ciu_en1_mirror);
790 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), cvmx_interrupt_ciu_en1_mirror);
842 cvmx_write_csr(CVMX_CIU_INTX_EN1(core * 2), cvmx_interrupt_ciu_en1_mirror);
843 cvmx_write_csr(CVMX_CIU_INTX_EN1((core * 2)+1), cvmx_interrupt_ciu_en1_mirror);
H A Dcvmx-ciu-defs.h293 static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset) function
307 cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
311 #define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16) macro

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