Searched refs:CVMX_CIU_INTX_EN0 (Results 1 - 6 of 6) sorted by relevance
/freebsd-10.2-release/sys/contrib/octeon-sdk/ |
H A D | cvmx-debug-uart.c | 247 irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(newcore * 2)); 249 cvmx_write_csr(CVMX_CIU_INTX_EN0(newcore * 2), irq_control.u64); 252 irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(oldcore * 2)); 254 cvmx_write_csr(CVMX_CIU_INTX_EN0(oldcore* 2), irq_control.u64);
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H A D | cvmx-interrupt.c | 420 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), cvmx_interrupt_ciu_en0_mirror); 794 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), cvmx_interrupt_ciu_en0_mirror); 840 cvmx_write_csr(CVMX_CIU_INTX_EN0(core * 2), cvmx_interrupt_ciu_en0_mirror); 841 cvmx_write_csr(CVMX_CIU_INTX_EN0((core * 2)+1), cvmx_interrupt_ciu_en0_mirror);
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H A D | cvmx-ciu-defs.h | 238 static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset) function 252 cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset); 256 #define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16) macro
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/freebsd-10.2-release/sys/mips/cavium/ |
H A D | ciu.c | 327 mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2)); 329 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), mask); 339 mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2)); 341 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), mask); 354 mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(core*2)); 359 cvmx_write_csr(CVMX_CIU_INTX_EN0(core*2), mask); 427 en0_mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2));
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H A D | octeon_machdep.c | 180 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 181 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 187 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
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/freebsd-10.2-release/sys/mips/cavium/octe/ |
H A D | ethernet.c | 261 en.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(core*2)); 263 cvmx_write_csr(CVMX_CIU_INTX_EN0(core*2), en.u64);
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