Searched refs:BaseOffs (Results 1 - 13 of 13) sorted by relevance

/freebsd-10.2-release/contrib/llvm/lib/Transforms/Scalar/
H A DCodeGenPrepare.cpp830 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) &&
852 if (BaseOffs)
853 OS << (NeedPlus ? " + " : "") << BaseOffs, NeedPlus = true;
972 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale;
1116 AddrMode.BaseOffs += ConstantOffset;
1122 AddrMode.BaseOffs -= ConstantOffset;
1131 AddrMode.BaseOffs += ConstantOffset;
1156 AddrMode.BaseOffs += ConstantOffset;
1180 AddrMode.BaseOffs
[all...]
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/
H A DBasicTargetTransformInfo.cpp147 AM.BaseOffs = BaseOffset;
158 AM.BaseOffs = BaseOffset;
H A DTargetLoweringBase.cpp1346 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1358 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1363 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/freebsd-10.2-release/contrib/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp283 DecomposeGEPExpression(const Value *V, int64_t &BaseOffs, argument
289 BaseOffs = 0;
350 BaseOffs += TD->getStructLayout(STy)->getElementOffset(FieldNo);
357 BaseOffs += TD->getTypeAllocSize(*GTI)*CIdx->getSExtValue();
377 BaseOffs += IndexOffset.getSExtValue()*Scale;
/freebsd-10.2-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1627 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1633 AM.BaseOffs%4 == 0;
1640 return isImmUs(AM.BaseOffs);
1643 return AM.Scale == 1 && AM.BaseOffs == 0;
1648 return isImmUs2(AM.BaseOffs);
1651 return AM.Scale == 2 && AM.BaseOffs == 0;
1655 return isImmUs4(AM.BaseOffs);
1658 return AM.Scale == 4 && AM.BaseOffs == 0;
/freebsd-10.2-release/contrib/llvm/include/llvm/Target/
H A DTargetLowering.h1121 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1123 /// If BaseOffs is zero, there is no base offset.
1129 int64_t BaseOffs;
1132 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1651 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7760 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7772 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7777 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/freebsd-10.2-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1961 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1970 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp330 if (!isInt<20>(AM.BaseOffs))
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp7075 AM.BaseOffs = Offset->getSExtValue();
7083 AM.BaseOffs = -Offset->getSExtValue();
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp10458 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10474 if (AM.BaseOffs)
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp13890 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13908 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))

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