Searched refs:Available (Results 1 - 7 of 7) sorted by relevance
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.cpp | 291 Available.push(SU); 316 DEBUG(dbgs() << "*** " << Available.getName() << " cycle " 353 if (Available.empty()) 371 Available.push(SU); 380 if (Available.isInQueue(SU)) 381 Available.remove(Available.find(SU)); 395 for (unsigned i = 0; Available.empty(); ++i) { 402 if (Available.size() == 1) 403 return *Available [all...] |
H A D | HexagonMachineScheduler.h | 137 ReadyQueue Available; member in struct:llvm::ConvergingVLIWScheduler::SchedBoundary 156 DAG(0), SchedModel(0), Available(ID, Name+".A"), 173 return Available.getID() == ConvergingVLIWScheduler::TopQID;
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/freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.cpp | 66 (Available[CurInstKind].empty()); 68 (!Available[IDFetch].empty() || !Available[IDOther].empty()); 70 if (CurInstKind == IDAlu && !Available[IDFetch].empty()) { 77 (FetchInstCount + Available[IDFetch].size()); 84 // Available[IDFetch].size() * 2 : GPRs required in the Fetch clause 90 unsigned NearRegisterRequirement = 2 * Available[IDFetch].size(); 176 MoveUnits(Pending[IDFetch], Available[IDFetch]); 204 Available[IDOther].push_back(SU); 456 std::vector<SUnit *> &AQ = Available[QI [all...] |
H A D | R600MachineScheduler.h | 54 std::vector<SUnit *> Available[IDLast], Pending[IDLast]; member in class:llvm::R600SchedStrategy
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/freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
H A D | MachineScheduler.cpp | 1445 ReadyQueue Available; member in struct:__anon2288::GenericScheduler::SchedBoundary 1508 Available.clear(); 1532 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"), 1544 return Available.getID() == GenericScheduler::TopQID; 1860 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) { 1912 DEBUG(dbgs() << Available.getName() << " RemLatency SU(" 1929 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: " 1940 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: " 1965 // ILat = max N.depth for N in Available|Pendin [all...] |
H A D | RegisterScavenging.cpp | 380 BitVector Available = getRegsAvailable(RC); local 381 Available &= Candidates; 382 if (Available.any()) 383 Candidates = Available;
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/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 372 BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass); local 374 Available &= Candidates; 383 Reg = Available.find_first(); 395 Available.reset(Reg); 399 SpReg = Available.find_first(); 411 Available.reset(SpReg);
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