Searched refs:AVIVO_D1GRPH_UPDATE (Results 1 - 4 of 4) sorted by relevance

/freebsd-10.2-release/sys/dev/drm2/radeon/
H A Drs600.c133 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
138 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
148 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
156 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
159 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
H A Drv770.c52 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
57 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
74 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
82 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
85 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
H A Drv515.c360 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
363 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
409 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
412 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
420 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
H A Dr500_reg.h420 #define AVIVO_D1GRPH_UPDATE 0x6144 macro

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