Searched refs:mcr (Results 1 - 25 of 43) sorted by relevance

12

/freebsd-10.1-release/sys/arm/arm/
H A Dcpufunc_asm_arm11.S47 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
49 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
50 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
60 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
66 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
84 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
85 mcr p1
[all...]
H A Dcpufunc_asm_armv4.S47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
52 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
57 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
62 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
70 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
76 mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */
H A Dcpufunc_asm_armv6.S52 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
54 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
56 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
70 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
81 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
82 mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */
83 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
101 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
115 mcr p1
[all...]
H A Dcpufunc_asm_arm11x6.S69 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
83 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
104 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
105 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
109 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
113 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
118 mcr p1
[all...]
H A Dcpufunc_asm_fa526.S43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */
44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */
45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */
46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */
48 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
71 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */
79 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/
85 mcr p1
[all...]
H A Dcpufunc_asm_arm10.S49 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
59 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
60 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
88 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
89 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
93 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
104 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
113 mcr p1
[all...]
H A Dcpufunc_asm_pj4b.S43 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
47 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
48 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
53 mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */
58 mcr p15, 0, r0, c7, c5, 6 /* flush entrie branch target cache */
63 mcr p15, 0, r0, c7, c5, 7 /* flush branch target cache by VA */
80 mcr p15, 1, r0, c15, c1, 0
90 mcr p15, 1, r0, c15, c1, 1
99 mcr p15, 1, r0, c15, c2, 0
109 mcr p1
[all...]
H A Dcpufunc_asm_xscale.S148 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
149 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
156 mcr p15, 0, r0, c2, c0, 0
159 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
162 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
179 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
180 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
188 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
193 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
198 mcr p1
[all...]
H A Dcpufunc_asm_armv5.S50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
52 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
76 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
77 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
81 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
92 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
101 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
105 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
108 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
126 mcr p1
[all...]
H A Dcpufunc_asm_xscale_c3.S148 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
160 mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */
169 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
186 1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */
188 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
195 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
208 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
209 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
216 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
229 1: mcr p1
[all...]
H A Dcpufunc_asm_armv5_ec.S60 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
63 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
65 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
87 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
88 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
103 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
110 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
128 mcr p1
[all...]
H A Dcpufunc_asm.S108 mcr p15, 0, r0, c1, c0, 0
114 mcr p15, 0, r0, c3, c0, 0
182 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
184 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */
186 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
187 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
190 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
191 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
H A Dcpufunc_asm_arm9.S48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
82 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
83 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
97 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
106 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
144 mcr p1
[all...]
H A Dcpufunc_asm_armv7.S73 mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */
76 mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/
78 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
88 mcr p15, 0, r0, c8, c3, 0 /* flush Unified TLB all entries Inner Shareable */
89 mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */
91 mcr p15, 0, r0, c8, c7, 0 /* flush Unified TLB all entries */
92 mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
103 mcr p15, 0, r0, c8, c3, 3 /* flush Unified TLB single entry Inner Shareable */
104 mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */
106 mcr p1
[all...]
H A Dcpufunc_asm_sheeva.S49 mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */
53 mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */
54 mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */
59 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
61 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
63 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
92 mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
93 mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
105 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
135 mcr p1
[all...]
H A Dlocore.S142 mcr p15, 0, r2, c1, c0, 0
199 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
200 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
204 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
209 mcr p15, 0, r0, c3, c0, 0
223 mcr p15, 0, r0, c1, c0, 0
363 mcr p15, 0, r2, c1, c0, 0
380 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
381 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
384 mcr p1
[all...]
H A Dswtch.S158 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */
204 mcr p15, 0, r5, c13, c0, 4
216 mcr p15, 0, r6, c13, c0, 3
242 mcr p15, 0, r1, c13, c0, 4
297 mcr p15, 0, r9, c13, c0, 3
368 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
/freebsd-10.1-release/sys/dev/uart/
H A Duart_dev_ns8250.h39 uint8_t mcr; member in struct:ns8250_softc
H A Duart_dev_lpc.c387 uint8_t mcr; member in struct:lpc_ns8250_softc
449 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR);
480 if (lpc_ns8250->mcr & MCR_DTR)
482 if (lpc_ns8250->mcr & MCR_RTS)
683 uint8_t lsr, mcr, ier; local
692 mcr = MCR_IE;
697 mcr |= MCR_DTR | MCR_RTS;
724 uart_setreg(bas, REG_MCR, mcr);
740 uart_setreg(bas, REG_MCR, mcr);
770 uart_setreg(bas, REG_MCR, mcr);
[all...]
H A Duart_dev_ns8250.c416 ns8250->mcr = uart_getreg(bas, REG_MCR);
447 if (ns8250->mcr & MCR_DTR)
449 if (ns8250->mcr & MCR_RTS)
692 uint8_t lsr, mcr, ier; local
701 mcr = MCR_IE;
706 mcr |= MCR_DTR | MCR_RTS;
733 uart_setreg(bas, REG_MCR, mcr);
749 uart_setreg(bas, REG_MCR, mcr);
779 uart_setreg(bas, REG_MCR, mcr);
788 uart_setreg(bas, REG_MCR, mcr);
[all...]
/freebsd-10.1-release/sys/arm/mv/armadaxp/
H A Dmptramp.S34 mcr p15, 0, r0, c7, c7, 0
/freebsd-10.1-release/usr.sbin/bhyve/
H A Duart_emul.c103 uint8_t mcr; /* Modem control register (R/W) */ member in struct:uart_softc
346 if ((sc->mcr & MCR_LOOPBACK) != 0) {
384 if (sc->mcr & MCR_LOOPBACK) {
428 sc->mcr = value & 0x1F;
431 if (sc->mcr & MCR_LOOPBACK) {
436 if (sc->mcr & MCR_RTS)
438 if (sc->mcr & MCR_DTR)
440 if (sc->mcr & MCR_OUT1)
442 if (sc->mcr & MCR_OUT2)
538 reg = sc->mcr;
[all...]
/freebsd-10.1-release/sys/dev/vte/
H A Dif_vte.c1232 uint16_t mcr; local
1237 mcr = CSR_READ_2(sc, VTE_MCR0);
1238 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX);
1240 mcr |= MCR0_FULL_DUPLEX;
1243 mcr |= MCR0_FC_ENB;
1251 mcr |= MCR0_FC_ENB;
1254 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1587 uint16_t mcr; local
1590 mcr = CSR_READ_2(sc, VTE_MCR1);
1591 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESE
1807 uint16_t mcr; local
1834 uint16_t mcr; local
1947 uint16_t mchash[4], mcr; local
[all...]
/freebsd-10.1-release/sys/dev/ubsec/
H A Dubsec.c646 struct ubsec_mcr *mcr; local
655 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
656 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
1777 struct ubsec_mcr *mcr; local
1789 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1792 mcr->mcr_pkts = htole16(1);
1793 mcr->mcr_flags = 0;
1794 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1795 mcr->mcr_ipktbuf.pb_addr = mcr
2147 struct ubsec_mcr *mcr; local
2349 struct ubsec_mcr *mcr; local
2547 struct ubsec_mcr *mcr; local
2763 ubsec_dump_mcr(struct ubsec_mcr *mcr) argument
[all...]
/freebsd-10.1-release/sys/boot/arm/uboot/
H A Dstart.S51 mcr p15, 0, r2, c1, c0, 0

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