Searched refs:c8 (Results 1 - 16 of 16) sorted by relevance

/freebsd-10.1-release/sys/arm/arm/
H A Dcpufunc_asm_armv4.S47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
52 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
57 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
62 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
H A Dcpufunc_asm_arm11.S49 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
86 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
99 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
105 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
111 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
117 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
H A Dcpufunc_asm_arm10.S51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
59 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
60 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
248 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
H A Dcpufunc_asm_armv7.S76 mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/
78 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
88 mcr p15, 0, r0, c8, c3, 0 /* flush Unified TLB all entries Inner Shareable */
91 mcr p15, 0, r0, c8, c7, 0 /* flush Unified TLB all entries */
103 mcr p15, 0, r0, c8, c3, 3 /* flush Unified TLB single entry Inner Shareable */
106 mcr p15, 0, r0, c8, c7, 1 /* flush Unified TLB single entry */
290 mcr p15, 0, r0, c8, c3, 0 /* and flush the I+D tlbs Inner Sharable */
292 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
H A Dcpufunc_asm_arm9.S50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
235 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
H A Dcpufunc_asm_fa526.S51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
71 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */
221 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
H A Dcpufunc_asm_armv6.S56 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
H A Dcpufunc_asm_pj4b.S48 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
H A Dcpufunc_asm_xscale.S159 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
179 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
180 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
500 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
H A Dlocore.S200 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
381 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
460 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
H A Dcpufunc_asm_arm11x6.S119 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
H A Dcpufunc_asm_xscale_c3.S377 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
412 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
H A Dcpufunc_asm_armv5.S52 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
H A Dcpufunc_asm_armv5_ec.S67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
H A Dcpufunc_asm_sheeva.S63 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
/freebsd-10.1-release/lib/libmp/tests/
H A Dlegacy_test.c35 MINT *c0, *c1, *c2, *c3, *c5, *c6, *c8, *c10, *c14, *c15, *c25, \ variable
104 testmcmp(t0, c8, "mdiv0");
107 mp_mdiv(c10, c8, t0, t1);
112 testmcmp(t0, c8, "sdiv0");
139 testmcmp(t0, c8, "pow0");
143 testmcmp(t0, c8, "rpow0");
169 c8 = mp_itom(8);
198 mp_mfree(c8);

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