/freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
H A D | PHIEliminationUtils.h | 17 /// SrcReg when following the CFG edge to SuccMBB. This needs to be after 18 /// any def of SrcReg, but before any subsequent point where control flow 22 unsigned SrcReg);
|
H A D | RegisterCoalescer.h | 35 /// SrcReg - the virtual register that will be coalesced into dstReg. 36 unsigned SrcReg; member in class:llvm::CoalescerPair 42 /// SrcIdx - The sub-register index of the old SrcReg in the new coalesced 52 /// Flipped - True when DstReg and SrcReg are reversed from the original 58 /// SrcReg and DstReg. 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible 105 unsigned getSrcReg() const { return SrcReg; } 111 /// getSrcIdx - Return the subregister index that SrcReg wil [all...] |
H A D | PHIEliminationUtils.cpp | 17 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg 19 // SrcReg, but before any subsequent point where control flow might jump out of 23 unsigned SrcReg) { 37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg), 22 findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB, unsigned SrcReg) argument
|
H A D | PHIElimination.cpp | 358 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); local 361 isImplicitlyDefined(SrcReg, MRI); 362 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && 378 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); 392 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 398 .addReg(SrcReg, 0, SrcSubReg); 402 // We only need to update the LiveVariables kill of SrcReg if this was the 403 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live 406 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] && 407 !LV->isLiveOut(SrcReg, opBloc [all...] |
H A D | OptimizePHIs.cpp | 99 unsigned SrcReg = MI->getOperand(i).getReg(); local 100 if (SrcReg == DstReg) 102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 120 SingleValReg = SrcReg;
|
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 43 unsigned DestReg, unsigned SrcReg, 46 .addReg(SrcReg, getKillRegState(KillSrc))); 47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 53 unsigned SrcReg, bool isKill, int FI, 57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 58 isARMLowRegister(SrcReg))) && "Unknown regclass!"); 61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 62 isARMLowRegister(SrcReg))) { 74 .addReg(SrcReg, getKillRegState(isKill)) 41 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
H A D | Thumb1InstrInfo.h | 44 unsigned DestReg, unsigned SrcReg, 48 unsigned SrcReg, bool isKill, int FrameIndex,
|
H A D | Thumb2InstrInfo.h | 45 unsigned DestReg, unsigned SrcReg, 50 unsigned SrcReg, bool isKill, int FrameIndex,
|
/freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 142 unsigned SrcReg = Src.getReg(); local 145 TargetRegisterInfo::isVirtualRegister(SrcReg)) { 149 PeepholeMap[DstReg] = SrcReg; 164 unsigned SrcReg = Src2.getReg(); local 165 PeepholeMap[DstReg] = SrcReg; 181 unsigned SrcReg = Src1.getReg(); local 183 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/); 193 unsigned SrcReg = Src.getReg(); local 196 TargetRegisterInfo::isVirtualRegister(SrcReg)) { 200 PeepholeMap[DstReg] = SrcReg; 216 unsigned SrcReg = Src.getReg(); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 36 unsigned DestReg, unsigned SrcReg, bool KillSrc) const { 39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); 46 .addReg(SrcReg, getKillRegState(KillSrc)); 49 .addReg(SrcReg, getKillRegState(KillSrc)); 52 .addReg(SrcReg, getKillRegState(KillSrc)); 55 .addReg(SrcReg, getKillRegState(KillSrc)); 58 .addReg(SrcReg, getKillRegState(KillSrc)); 61 .addReg(SrcReg, getKillRegState(KillSrc)); 67 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, argument 82 SrcReg 34 copyPhysReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument [all...] |
H A D | NVPTXInstrInfo.h | 45 * unsigned SrcReg, bool isKill, int FrameIndex, 55 unsigned DestReg, unsigned SrcReg, bool KillSrc) const; 56 virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
|
/freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 72 unsigned SrcReg, bool isKill, int FrameIdx, 99 unsigned &SrcReg, unsigned &DstReg, 137 unsigned DestReg, unsigned SrcReg, 142 unsigned SrcReg, bool isKill, int FrameIndex, 207 unsigned &SrcReg, unsigned &SrcReg2, 211 unsigned SrcReg, unsigned SrcReg2,
|
H A D | PPCInstrInfo.cpp | 90 unsigned &SrcReg, unsigned &DstReg, 96 SrcReg = MI.getOperand(1).getReg(); 535 unsigned DestReg, unsigned SrcReg, 538 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 540 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 542 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 544 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 546 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 548 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 556 .addReg(SrcReg) 89 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument 533 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 563 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument 657 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 1067 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument 1095 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.h | 43 unsigned DestReg, unsigned SrcReg, 48 unsigned SrcReg, bool isKill, int FrameIndex, 97 unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
|
H A D | AArch64InstrInfo.cpp | 43 unsigned DestReg, unsigned SrcReg, 47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) { 50 .addReg(SrcReg) 53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { 56 .addReg(SrcReg) 60 assert(AArch64::GPR64RegClass.contains(SrcReg)); 64 .addReg(SrcReg); 65 } else if (SrcReg == AArch64::NZCV) { 71 if(AArch64::GPR64RegClass.contains(SrcReg)){ 75 assert(AArch64::FPR64RegClass.contains(SrcReg)); 41 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 396 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 631 emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc dl, const TargetInstrInfo &TII, unsigned DstReg, unsigned SrcReg, unsigned ScratchReg, int64_t NumBytes, MachineInstr::MIFlag MIFlags) argument [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 84 unsigned DestReg, unsigned SrcReg, 89 if (Mips::GPR32RegClass.contains(SrcReg)) 91 else if (Mips::CCRRegClass.contains(SrcReg)) 93 else if (Mips::FGR32RegClass.contains(SrcReg)) 95 else if (Mips::HI32RegClass.contains(SrcReg)) 96 Opc = Mips::MFHI, SrcReg = 0; 97 else if (Mips::LO32RegClass.contains(SrcReg)) 98 Opc = Mips::MFLO, SrcReg = 0; 99 else if (Mips::HI32DSPRegClass.contains(SrcReg)) 101 else if (Mips::LO32DSPRegClass.contains(SrcReg)) 82 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 177 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument 479 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; local 500 unsigned SrcReg = I->getOperand(1).getReg(); local [all...] |
H A D | MipsInstrInfo.h | 88 unsigned SrcReg, bool isKill, int FrameIndex, 91 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); 104 unsigned SrcReg, bool isKill, int FrameIndex, 86 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
H A D | MipsSEInstrInfo.h | 49 unsigned DestReg, unsigned SrcReg, 54 unsigned SrcReg, bool isKill, int FrameIndex,
|
/freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.h | 57 unsigned DestReg, unsigned SrcReg, 62 unsigned SrcReg, bool isKill,
|
/freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.h | 80 unsigned DestReg, unsigned SrcReg, 85 unsigned SrcReg, bool isKill, int FrameIndex,
|
H A D | SparcInstrInfo.cpp | 280 unsigned DestReg, unsigned SrcReg, 292 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 294 .addReg(SrcReg, getKillRegState(KillSrc)); 295 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 297 .addReg(SrcReg, getKillRegState(KillSrc)); 298 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { 301 .addReg(SrcReg, getKillRegState(KillSrc)); 308 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { 312 .addReg(SrcReg, getKillRegState(KillSrc)); 336 unsigned Src = TRI->getSubReg(SrcReg, subRegId 278 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 348 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.h | 67 unsigned DestReg, unsigned SrcReg, 72 unsigned SrcReg, bool isKill, int FrameIndex,
|
H A D | XCoreRegisterInfo.h | 34 unsigned SrcReg, int Offset, DebugLoc dl) const;
|
/freebsd-10.1-release/contrib/llvm/lib/Target/R600/ |
H A D | SIInstrInfo.cpp | 41 unsigned DestReg, unsigned SrcReg, 47 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); 88 if (!I->readsRegister(SrcReg)) 97 assert(AMDGPU::SReg_32RegClass.contains(SrcReg)); 99 .addReg(SrcReg, getKillRegState(KillSrc)); 103 assert(AMDGPU::SReg_64RegClass.contains(SrcReg)); 105 .addReg(SrcReg, getKillRegState(KillSrc)); 109 assert(AMDGPU::SReg_128RegClass.contains(SrcReg)); 114 assert(AMDGPU::SReg_256RegClass.contains(SrcReg)); 119 assert(AMDGPU::SReg_512RegClass.contains(SrcReg)); 39 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 121 unsigned SrcReg = MI->getOperand(1).getReg(); local 123 bool SrcIsHigh = isHighReg(SrcReg); 128 DestReg, SrcReg, SystemZ::LR, 32, 157 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR 158 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg 160 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR). 161 // KillSrc is true if this move is the last use of SrcReg. 165 unsigned SrcReg, unsigned LowLowOpcode, 169 bool SrcIsHigh = isHighReg(SrcReg); 178 .addReg(SrcReg, getKillRegStat 162 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, unsigned LowLowOpcode, unsigned Size, bool KillSrc) const argument 399 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument 442 removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI) argument 483 optimizeCompareInstr(MachineInstr *Compare, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument 553 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 589 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 692 unsigned SrcReg = Src.getReg(); local [all...] |