/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | VirtRegMap.h | 153 /// records virtReg is a split live interval from SReg. 154 void setIsSplitFromReg(Register virtReg, Register SReg) { argument 155 Virt2SplitMap[virtReg.id()] = SReg; 156 if (hasShape(SReg)) { 157 Virt2ShapeMap[virtReg.id()] = getShape(SReg);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 100 unsigned getDPRLaneFromSPR(unsigned SReg); 115 unsigned getPrefSPRLane(unsigned SReg); 144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { argument 145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, 153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { argument 154 if (!Register::isVirtualRegister(SReg)) 155 return getDPRLaneFromSPR(SReg); 157 MachineInstr *MI = MRI->getVRegDef(SReg); 159 MachineOperand *MO = MI->findRegisterDefOperand(SReg); 165 SReg [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | LivePhysRegs.cpp | 263 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) { 264 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
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H A D | RegisterScavenging.cpp | 546 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI); local 549 if (!isRegUsed(SReg)) { 550 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); 551 return SReg; 557 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); 561 << printReg(SReg, TRI) << "\n"); 563 return SReg; 654 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), local 656 MRI.replaceRegWith(VReg, SReg); 658 return SReg; 694 Register SReg = scavengeVReg(MRI, RS, Reg, true); local 720 Register SReg = scavengeVReg(MRI, RS, Reg, false); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIPreEmitPeephole.cpp | 119 Register SReg; local 121 SReg = Op2.getReg(); 125 if (M->definesRegister(SReg, TRI)) 127 if (M->modifiesRegister(SReg, TRI)) 129 ReadsSreg |= M->readsRegister(SReg, TRI); 168 if (SReg == ExecReg) {
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H A D | SIShrinkInstructions.cpp | 761 Register SReg = Src2->getReg(); local 762 if (SReg.isVirtual()) { 763 MRI.setRegAllocationHint(SReg, 0, VCCReg); 766 if (SReg != VCCReg)
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H A D | SIInstrInfo.cpp | 1057 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local 1058 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) 1065 .addReg(SReg); 1070 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local 1072 : AMDGPU::S_CSELECT_B64), SReg) 1080 .addReg(SReg); 1084 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local 1086 : AMDGPU::S_CSELECT_B64), SReg) 1094 .addReg(SReg); 1100 Register SReg local 1114 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local 1126 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local 1144 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local [all...] |
/netbsd-current/external/apache2/llvm/dist/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | MemRegion.h | 992 ParamVarRegion(const Expr *OE, unsigned Idx, const MemRegion *SReg) argument 993 : VarRegion(SReg, ParamVarRegionKind), OriginExpr(OE), Index(Idx) { 994 assert(!cast<StackSpaceRegion>(SReg)->getStackFrame()->inTopFrame()); 998 unsigned Idx, const MemRegion *SReg); 1217 const SubRegion *SReg) 1218 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) { 1223 bool IsVirtual, const MemRegion *SReg); 1254 CXXDerivedObjectRegion(const CXXRecordDecl *DerivedD, const SubRegion *SReg) argument 1255 : TypedValueRegion(SReg, CXXDerivedObjectRegionKind), DerivedD(DerivedD) { 1260 assert(SReg 1216 CXXBaseObjectRegion(const CXXRecordDecl *RD, bool IsVirtual, const SubRegion *SReg) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
H A D | MemRegion.cpp | 307 unsigned Idx, const MemRegion *SReg) { 311 ID.AddPointer(SReg); 395 const MemRegion *SReg) { 398 ID.AddPointer(SReg); 407 const MemRegion *SReg) { 409 ID.AddPointer(SReg); 306 ProfileRegion(llvm::FoldingSetNodeID &ID, const Expr *OE, unsigned Idx, const MemRegion *SReg) argument 392 ProfileRegion(llvm::FoldingSetNodeID &ID, const CXXRecordDecl *RD, bool IsVirtual, const MemRegion *SReg) argument 405 ProfileRegion(llvm::FoldingSetNodeID &ID, const CXXRecordDecl *RD, const MemRegion *SReg) argument
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/netbsd-current/external/gpl3/binutils.old/dist/opcodes/ |
H A D | i386-opc.h | 782 SReg, /* Segment register */ 719 SReg, /* Segment register */ enumerator in enum:operand_class
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H A D | i386-gen.c | 495 "Class=SReg" }, 748 CLASS (SReg),
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/netbsd-current/external/gpl3/binutils/dist/opcodes/ |
H A D | i386-opc.h | 782 SReg, /* Segment register */ enumerator in enum:operand_class
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H A D | i386-gen.c | 495 "Class=SReg" }, 748 CLASS (SReg),
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/netbsd-current/external/gpl3/gdb.old/dist/opcodes/ |
H A D | i386-opc.h | 742 SReg, /* Segment register */ enumerator in enum:operand_class
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H A D | i386-gen.c | 465 "Class=SReg" }, 711 CLASS (SReg),
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/netbsd-current/external/gpl3/gdb/dist/opcodes/ |
H A D | i386-opc.h | 787 SReg, /* Segment register */ enumerator in enum:operand_class
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H A D | i386-gen.c | 683 CLASS (SReg),
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 1325 SReg = MF.getRegInfo().createVirtualRegister(RC); 1329 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) 1334 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 1360 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 4861 unsigned SReg = Inst.getOperand(1).getReg(); local 4869 if (DReg == SReg) { 4877 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); 4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); 4908 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); 4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); 4924 unsigned SReg = Inst.getOperand(1).getReg(); local 4936 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); 4941 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); 4950 TOut.emitRRI(Mips::SRL, DReg, SReg, 4986 unsigned SReg = Inst.getOperand(1).getReg(); local 5049 unsigned SReg = Inst.getOperand(1).getReg(); local [all...] |
/netbsd-current/external/gpl3/binutils.old/dist/gas/config/ |
H A D | tc-i386-intel.c | 323 if (i386_regtab[reg_num].reg_type.bitfield.class == SReg 1063 if (i386_regtab[expP->X_add_number].reg_type.bitfield.class != SReg)
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H A D | tc-i386.c | 3001 case SReg: 3143 || x->types[j].bitfield.class == SReg 3250 { OPERAND_TYPE_SREG, "SReg" }, 7956 else if (i.types[0].bitfield.class == SReg) 8580 || i.types[op].bitfield.class == SReg 11461 if (*op_string == ':' && r->reg_type.bitfield.class == SReg) 12825 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) 12888 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
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/netbsd-current/external/gpl3/binutils/dist/gas/config/ |
H A D | tc-i386-intel.c | 323 if (i386_regtab[reg_num].reg_type.bitfield.class == SReg 1063 if (i386_regtab[expP->X_add_number].reg_type.bitfield.class != SReg)
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H A D | tc-i386.c | 3001 case SReg: 3143 || x->types[j].bitfield.class == SReg 3250 { OPERAND_TYPE_SREG, "SReg" }, 7956 else if (i.types[0].bitfield.class == SReg) 8580 || i.types[op].bitfield.class == SReg 11461 if (*op_string == ':' && r->reg_type.bitfield.class == SReg) 12825 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) 12888 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
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/netbsd-current/external/gpl3/gdb.old/dist/gas/config/ |
H A D | tc-i386-intel.c | 299 if (i386_regtab[reg_num].reg_type.bitfield.class == SReg 1008 if (i386_regtab[expP->X_add_number].reg_type.bitfield.class != SReg)
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H A D | tc-i386.c | 3207 || x->types[j].bitfield.class == SReg 3305 { OPERAND_TYPE_SREG, "SReg" }, 7656 else if (i.types[0].bitfield.class == SReg) 8337 || i.types[op].bitfield.class == SReg 11227 if (*op_string == ':' && r->reg_type.bitfield.class == SReg) 12537 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) 12600 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
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