Searched refs:PACKET0 (Results 1 - 14 of 14) sorted by relevance

/freebsd-10.1-release/sys/dev/drm2/radeon/
H A Dr300.c186 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
188 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
191 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
193 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
196 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
200 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
203 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
206 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
208 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
239 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNT
[all...]
H A Drv515.c71 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
77 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
79 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
81 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
83 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
85 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
87 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
89 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93 radeon_ring_write(ring, PACKET0(WAIT_UNTI
[all...]
H A Dr200.c108 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
116 radeon_ring_write(ring, PACKET0(0x720, 2));
123 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
H A Dr420.c214 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
228 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
H A Dr100.c815 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
817 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
820 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
822 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
825 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
828 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
830 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
903 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
905 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
940 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNT
[all...]
H A Dni.c1943 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
1947 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1951 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
H A Dnid.h489 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
H A Dr300d.h63 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
H A Drv515d.h203 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
H A Dsid.h798 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
H A Dr100d.h62 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
H A Devergreend.h996 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
H A Dr600d.h1158 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
H A Dr600.c2596 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));

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