Searched refs:Outs (Results 1 - 25 of 36) sorted by relevance

12

/freebsd-10.1-release/contrib/llvm/lib/CodeGen/
H A DCallingConvLower.cpp86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
90 MVT VT = Outs[i].VT;
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
104 MVT VT = Outs[i].VT;
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
120 unsigned NumOps = Outs
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
117 EVT VT = Outs[i].VT;
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
132 &Outs,
136 unsigned NumOps = Outs.size();
147 EVT ArgVT = Outs[i].VT;
148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
131 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize) argument
H A DHexagonCallingConvLower.h84 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DHexagonISelLowering.h90 SmallVectorImpl<ISD::OutputArg> &Outs,
134 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DHexagonISelLowering.cpp315 const SmallVectorImpl<ISD::OutputArg> &Outs,
327 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
398 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
407 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
434 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
436 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
445 Outs, OutVals, Ins, DAG);
473 ISD::ArgFlagsTy Flags = Outs[
313 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
1682 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h131 const SmallVectorImpl<ISD::OutputArg> &Outs,
164 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DMSP430ISelLowering.cpp270 const SmallVectorImpl<ISD::OutputArg> &Outs) {
271 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
355 const SmallVectorImpl<ISD::OutputArg> &Outs) {
356 State.AnalyzeReturn(Outs, RetCC_MSP430);
399 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
417 Outs, OutVals, Ins, dl, DAG, InVals);
527 const SmallVectorImpl<ISD::OutputArg> &Outs,
535 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
543 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
269 AnalyzeVarArgs(CCState &State, const SmallVectorImpl<ISD::OutputArg> &Outs) argument
354 AnalyzeRetResult(CCState &State, const SmallVectorImpl<ISD::OutputArg> &Outs) argument
525 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
578 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h123 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DSparcISelLowering.cpp173 const SmallVectorImpl<ISD::OutputArg> &Outs,
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
247 const SmallVectorImpl<ISD::OutputArg> &Outs,
258 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
686 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
702 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc3
171 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
182 LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
245 LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
1006 fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, ArrayRef<ISD::OutputArg> Outs) argument
[all...]
/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h250 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
261 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-10.1-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h130 const SmallVectorImpl<ISD::OutputArg> &Outs,
198 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DXCoreISelLowering.cpp881 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
901 Outs, OutVals, Ins, dl, DAG, InVals);
913 const SmallVectorImpl<ISD::OutputArg> &Outs,
928 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1263 const SmallVectorImpl<ISD::OutputArg> &Outs,
1267 return CCInfo.CheckReturn(Outs, RetCC_XCore);
1273 const SmallVectorImpl<ISD::OutputArg> &Outs,
1286 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
910 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1261 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
1271 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
/freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h555 const SmallVectorImpl<ISD::OutputArg> &Outs,
561 const SmallVectorImpl<ISD::OutputArg> &Outs,
602 const SmallVectorImpl<ISD::OutputArg> &Outs,
611 const SmallVectorImpl<ISD::OutputArg> &Outs,
619 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DPPCISelLowering.cpp2868 &Outs,
2875 unsigned NumOps = Outs.size();
2886 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2887 EVT ArgVT = Outs[i].VT;
3521 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
3537 isTailCall, Outs, OutVals, Ins,
3541 isTailCall, Outs, OutVals, Ins,
3546 isTailCall, Outs, OutVals, Ins,
3554 const SmallVectorImpl<ISD::OutputArg> &Outs,
2863 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, bool isPPC64, bool isVarArg, unsigned CC, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, unsigned &nAltivecParamsAtEnd) argument
3551 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3786 LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4167 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4516 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
4527 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.h350 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
362 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
536 const SmallVectorImpl<ISD::OutputArg> &Outs,
542 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-10.1-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h131 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DNVPTXISelLowering.cpp74 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
348 const SmallVectorImpl<ISD::OutputArg> &Outs,
419 if (Outs[OIdx].Flags.isByVal() == false) {
431 // update the index for Outs
439 assert((getValueType(Ty) == Outs[OIdx].VT ||
440 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
460 unsigned align = Outs[OIdx].Flags.getByValAlign();
523 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
548 // Args.size() and Outs
347 getPrototype(Type *retTy, const ArgListTy &Args, const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment, const ImmutableCallSite *CS) const argument
1695 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h223 const SmallVectorImpl<ISD::OutputArg> &Outs,
254 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DAArch64ISelLowering.cpp1247 const SmallVectorImpl<ISD::OutputArg> &Outs,
1258 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1323 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
1336 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1342 Outs, OutVals, Ins, DAG);
1353 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1399 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1633 const SmallVectorImpl<ISD::OutputArg> &Outs,
1245 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
1628 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, bool IsCalleeStructRet, bool IsCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...]
/freebsd-10.1-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp68 SmallVector<ISD::OutputArg, 4> Outs; local
69 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
72 Outs, Fn->getContext());
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp115 SmallVectorImpl<MachineInstr*> &Outs);
368 SmallVectorImpl<MachineInstr*> &Outs) {
402 Outs.push_back(MI);
367 elideCopiesAndPHIs(MachineInstr *MI, SmallVectorImpl<MachineInstr*> &Outs) argument
H A DARMISelLowering.h522 const SmallVectorImpl<ISD::OutputArg> &Outs,
529 const SmallVectorImpl<ISD::OutputArg> &Outs,
535 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.h840 const SmallVectorImpl<ISD::OutputArg> &Outs,
913 const SmallVectorImpl<ISD::OutputArg> &Outs,
927 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-10.1-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.h83 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h244 const SmallVectorImpl<ISD::OutputArg> &Outs,

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