Searched refs:NextVA (Results 1 - 6 of 6) sorted by relevance

/freebsd-10.1-release/contrib/llvm/tools/clang/lib/AST/
H A DStmtIterator.cpp33 void StmtIteratorBase::NextVA() { function in class:StmtIteratorBase
/freebsd-10.1-release/contrib/llvm/tools/clang/include/clang/AST/
H A DStmtIterator.h63 void NextVA();
91 NextVA();
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.h415 CCValAssign &VA, CCValAssign &NextVA,
419 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
H A DARMFastISel.cpp2070 CCValAssign &NextVA = ArgLocs[++i]; local
2072 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2077 .addReg(NextVA.getLocReg(), RegState::Define)
2080 RegArgs.push_back(NextVA.getLocReg());
H A DARMISelLowering.cpp1409 CCValAssign &VA, CCValAssign &NextVA,
1418 if (NextVA.isRegLoc())
1419 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1421 assert(NextVA.isMemLoc());
1426 dl, DAG, NextVA,
2752 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, argument
2769 if (NextVA.isMemLoc()) {
2771 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2779 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1406 PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
/freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp380 CCValAssign &NextVA = ArgLocs[++i]; local
383 if (NextVA.isMemLoc()) {
385 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
391 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
820 CCValAssign &NextVA = ArgLocs[++i]; local
821 if (NextVA.isRegLoc()) {
822 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
825 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;

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