Searched refs:IndexReg (Results 1 - 13 of 13) sorted by relevance

/freebsd-10.1-release/contrib/llvm/lib/Target/X86/
H A DX86InstrBuilder.h49 unsigned IndexReg; member in struct:llvm::X86AddressMode
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
72 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
133 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
H A DX86AsmPrinter.cpp273 const MachineOperand &IndexReg = MI->getOperand(Op+2); local
283 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
299 assert(IndexReg.getReg() != X86::ESP &&
306 if (IndexReg.getReg()) {
333 const MachineOperand &IndexReg = MI->getOperand(Op+2); local
351 if (IndexReg.getReg()) {
364 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
H A DX86CodeEmitter.cpp482 const MachineOperand &IndexReg = MI.getOperand(Op+2);
489 assert(IndexReg.getReg() == 0 && Is64BitMode &&
510 IndexReg.getReg() == 0 &&
548 assert(IndexReg.getReg() != X86::ESP &&
549 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
582 if (IndexReg.getReg())
583 IndexRegNo = getX86RegNum(IndexReg.getReg());
590 if (IndexReg.getReg())
591 IndexRegNo = getX86RegNum(IndexReg.getReg());
616 const MachineOperand &IndexReg
[all...]
H A DX86ISelDAGToDAG.cpp60 SDValue IndexReg; member in struct:__anon2661::X86ISelAddressMode
72 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
83 IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
111 << "IndexReg ";
112 if (IndexReg.getNode() != 0)
113 IndexReg.getNode()->dump();
236 Index = AM.IndexReg;
737 AM.Base_Reg = AM.IndexReg;
749 AM.IndexReg.getNode() == 0 &&
808 AM.IndexReg
[all...]
H A DX86FastISel.cpp374 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
393 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
455 if (AM.IndexReg == 0) {
457 AM.IndexReg = getRegForValue(V);
458 return AM.IndexReg != 0;
541 unsigned IndexReg = AM.IndexReg; local
573 if (IndexReg == 0 &&
578 IndexReg = getRegForGEPIndex(Op).first;
579 if (IndexReg
[all...]
H A DX86ISelLowering.cpp15247 .addReg(/*IndexReg=*/0)
15904 AM.IndexReg = Op.getImm();
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp204 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon2620::X86AsmParser::IntelExprStateMachine
213 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
218 unsigned getIndexReg() { return IndexReg; }
246 // If we already have a BaseReg, then assume this is the IndexReg with
251 assert (!IndexReg && "BaseReg/IndexReg already set!");
252 IndexReg = TmpReg;
282 // If we already have a BaseReg, then assume this is the IndexReg with
287 assert (!IndexReg && "BaseReg/IndexReg alread
643 unsigned IndexReg; member in struct:__anon2621::X86Operand::MemOp
1000 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(), void *OpDecl = 0) argument
1179 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1413 int IndexReg = SM.getIndexReg(); local
1824 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp176 const MCOperand &IndexReg = MI->getOperand(Op+2); local
190 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
197 if (IndexReg.getReg() || BaseReg.getReg()) {
202 if (IndexReg.getReg()) {
H A DX86IntelInstPrinter.cpp156 const MCOperand &IndexReg = MI->getOperand(Op+2); local
174 if (IndexReg.getReg()) {
188 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp222 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
226 (IndexReg.getReg() != 0 &&
227 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
237 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
241 (IndexReg.getReg() != 0 &&
242 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
252 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
256 (IndexReg.getReg() != 0 &&
257 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
373 const MCOperand &IndexReg local
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/R600/
H A DSIInstrInfo.h126 unsigned SavReg, unsigned IndexReg) const;
/freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp153 unsigned &IndexReg);
399 unsigned &IndexReg) {
421 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
422 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
486 unsigned IndexReg = 0; local
487 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
533 .addReg(Addr.Base.Reg).addReg(IndexReg);
605 unsigned IndexReg = 0; local
606 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
644 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
398 PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, unsigned &IndexReg) argument
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2337 unsigned IndexReg = MI->getOperand(3).getReg(); local
2347 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
2379 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);

Completed in 241 milliseconds