Searched refs:operands (Results 1 - 25 of 59) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/utils/TableGen/
H A DX86DisassemblerShared.h17 struct OperandSpecifier operands[X86_MAX_OPERANDS]; \
28 memset(operands, 0, sizeof(operands)); \
/freebsd-10.0-release/contrib/gcc/config/rs6000/
H A Ddarwin.md48 output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands);
49 output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands);
178 emit_insn (gen_macho_high_di (operands[0], operands[1]));
180 emit_insn (gen_macho_high_si (operands[0], operands[1]));
205 emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
207 emit_insn (gen_macho_low_si (operands[
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H A Drs6000.c609 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
2328 output_vec_const_move (rtx *operands)
2334 dest = operands[0];
2335 vec = operands[1];
2346 operands[1] = XEXP (splat_vec, 0);
2347 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2375 operands[1] = CONST_VECTOR_ELT (vec, 0);
2376 operands[2] = CONST_VECTOR_ELT (vec, 1);
3030 /* Make sure both operands are registers. */
3950 rs6000_eliminate_indexed_memrefs (rtx operands[
2320 output_vec_const_move(rtx *operands) argument
3940 rs6000_eliminate_indexed_memrefs(rtx operands[2]) argument
3963 rtx operands[2]; local
9341 expand_block_clear(rtx operands[]) argument
9436 expand_block_move(rtx operands[]) argument
9612 rs6000_output_load_multiple(rtx operands[3]) argument
12131 output_isel(rtx *operands) argument
13774 rtx operands[2]; local
13801 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); local
18087 output_call(rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number) argument
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/freebsd-10.0-release/contrib/binutils/opcodes/
H A Dia64-asmtab.h47 /* The operands of this instruction. Corresponds to the OPERANDS field
49 unsigned char operands[5]; member in struct:ia64_main_table
H A Dia64-opc.c339 o2 = elf64_ia64_operands + main_table[place].operands[2];
546 res->operands[0] = main_table[place].operands[0];
547 res->operands[1] = main_table[place].operands[1];
548 res->operands[2] = main_table[place].operands[2];
549 res->operands[3] = main_table[place].operands[3];
550 res->operands[
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H A Dia64-gen.c933 int i2627 = i && idesc->operands[0] == IA64_OPND_AR3;
934 int i28 = i && idesc->operands[1] == IA64_OPND_AR3;
935 int m2930 = m && idesc->operands[0] == IA64_OPND_AR3;
936 int m31 = m && idesc->operands[1] == IA64_OPND_AR3;
937 int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3;
938 int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3;
955 int i21 = idesc->operands[0] == IA64_OPND_B1;
956 int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2;
965 int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3;
966 int m33 = plain_mov && idesc->operands[
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H A Dalpha-dis.c128 /* Make two passes over the operands. First see if any of them
133 for (opindex = opcode->operands; *opindex != 0; opindex++)
154 if (opcode->operands[0] != 0)
157 /* Now extract and print the operands. */
159 for (opindex = opcode->operands; *opindex != 0; opindex++)
H A Dia64-dis.c143 if (idesc->operands[0])
147 for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
149 odesc = elf64_ia64_operands + idesc->operands[j];
H A Di386-gen.c104 char *name, *operands, *base_opcode, *extension_opcode; local
147 /* Find number of operands. */
148 operands = next_field (str, &str);
221 name, operands, base_opcode, extension_opcode,
/freebsd-10.0-release/contrib/binutils/gas/config/
H A Dtc-arm.c257 - Immediate operands do not require a # prefix.
268 - Immediate operands do not require a # prefix.
350 } operands[6]; member in struct:arm_it
521 unsigned char operands[8]; member in struct:asm_opcode
2086 Neon mnemonic, so long as all operands given have types. Types can also be
3937 /* Parser functions used exclusively in instruction operands. */
3969 instructions. Puts the result directly in inst.operands[i]. */
3981 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
3988 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
3989 inst.operands[
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H A Dtc-ia64.c26 - optional operands
5663 enum ia64_opnd opnd = idesc->operands[index];
5752 /* register operands: */
5807 /* indirect operands: */
5829 /* immediate operands: */
5833 bits = operand_width (idesc->operands[index]);
5907 fix->opnd = idesc->operands[index];
5942 bits = operand_width (idesc->operands[index]);
5953 bits = operand_width (idesc->operands[index]);
6029 bits = operand_width (idesc->operands[inde
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/freebsd-10.0-release/contrib/llvm/include/llvm/IR/
H A DOperandTraits.h12 // the operands in the most efficient manner.
38 static unsigned operands(const User*) { function in struct:llvm::FixedNumOperandTraits
47 /// OptionalOperandTraits - when the number of operands may change at runtime.
52 static unsigned operands(const User *U) { function in struct:llvm::OptionalOperandTraits
73 static unsigned operands(const User *U) { function in struct:llvm::VariadicOperandTraits
100 static unsigned operands(const User *U) { function in struct:llvm::HungoffOperandTraits
137 assert(i_nocapture < OperandTraits<CLASS>::operands(this) \
143 assert(i_nocapture < OperandTraits<CLASS>::operands(this) \
148 return OperandTraits<CLASS>::operands(this); \
/freebsd-10.0-release/tools/test/testfloat/
H A Dtestfloat.c54 int8 operands, roundingPrecision, roundingMode; local
69 operands = 0;
211 operands = 1;
216 operands = 2;
221 operands = 0;
260 if ( operands == 1 ) {
272 else if ( operands == 2 ) {
/freebsd-10.0-release/contrib/binutils/include/opcode/
H A Ds390.h51 operands are zeroes. */
57 match (and are presumably filled in by operands). */
64 operand table. They appear in the order which the operands must
66 unsigned char operands[6]; member in struct:s390_opcode
87 /* The operands table is an array of struct s390_operand. */
102 the operands field of the powerpc_opcodes table. */
H A Dppc.h33 operands are zeroes. */
39 match (and are presumably filled in by operands). */
48 operand table. They appear in the order which the operands must
50 unsigned char operands[8]; member in struct:powerpc_opcode
153 /* The operands table is an array of struct powerpc_operand. */
178 operand value is legal, *ERRMSG will be unchanged (most operands
206 the operands field of the powerpc_opcodes table. */
224 operands fields are identical. The assembler should call the
232 store instructions which want their operands to look like
267 assembler must count the number of operands remainin
310 unsigned int operands; member in struct:powerpc_macro
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H A Dalpha.h33 operands are zeroes. */
39 match (and are presumably filled in by operands). */
48 operand table. They appear in the order which the operands must
50 unsigned char operands[4]; member in struct:alpha_opcode
80 /* The operands table is an array of struct alpha_operand. */
110 operand value is legal, *ERRMSG will be unchanged (most operands
135 the operands field of the alpha_opcodes table. */
149 is used to support extended mnemonics, for which two operands fields
158 instructions which want their operands to look like "Ra,disp(Rb)". */
/freebsd-10.0-release/contrib/gcc/
H A Dgenemit.c322 int operands;
406 /* Find out how many operands this function has. */
407 operands = max_operand_vec (insn, 1);
408 if (max_dup_opno >= operands)
413 if (operands)
414 for (i = 0; i < operands; i++)
452 int operands;
460 /* Find out how many operands this function has. */
461 operands = max_operand_vec (expand, 1);
465 if (operands)
319 int operands; local
448 int operands; local
584 int operands; local
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H A Dtree-ssa-operands.h24 /* Interface to SSA operands. */
37 /* This represents the DEF operands of a stmt. */
45 /* This represents the USE operands of a stmt. */
95 /* Statement operands. */
99 /* Virtual operands (V_MAY_DEF, VUSE, and V_MUST_DEF). */
114 #define DEF_OPS(STMT) (stmt_ann (STMT)->operands.def_ops)
115 #define USE_OPS(STMT) (stmt_ann (STMT)->operands.use_ops)
116 #define VUSE_OPS(STMT) (stmt_ann (STMT)->operands.vuse_ops)
117 #define MAYDEF_OPS(STMT) (stmt_ann (STMT)->operands.maydef_ops)
118 #define MUSTDEF_OPS(STMT) (stmt_ann (STMT)->operands
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/freebsd-10.0-release/contrib/llvm/lib/IR/
H A DConstantsContext.h55 // allocate space for exactly two operands
76 // allocate space for exactly three operands
97 // allocate space for exactly two operands
118 // allocate space for exactly three operands
140 // allocate space for exactly three operands
239 // allocate space for exactly two operands
323 operands(ops.begin(), ops.end()), indices(inds.begin(), inds.end()) {}
327 std::vector<Constant*> operands; member in struct:llvm::ExprMapKeyType
333 this->operands == that.operands
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/freebsd-10.0-release/contrib/gcc/config/i386/
H A Di386.c8017 %b0 would print %al if operands[0] is reg 0.
8104 /* 387 opcodes don't get size suffixes if the operands are
8338 /* Avoid (%rip) for call operands. */
8361 /* These float cases don't actually occur as immediate operands. */
8612 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8614 that parallel "operands". */
8617 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8621 rtx op = operands[num];
8643 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8645 that parallel "operands"
8594 split_di(rtx operands[], int num, rtx lo_half[], rtx hi_half[]) argument
8625 split_ti(rtx operands[], int num, rtx lo_half[], rtx hi_half[]) argument
8664 output_387_binary_op(rtx insn, rtx *operands) argument
9015 output_fix_trunc(rtx insn, rtx *operands, int fisttp) argument
9079 output_fp_compare(rtx insn, rtx *operands, int eflags_p, int unordered_p) argument
9273 ix86_expand_move(enum machine_mode mode, rtx operands[]) argument
9386 ix86_expand_vector_move(enum machine_mode mode, rtx operands[]) argument
9416 ix86_expand_vector_move_misalign(enum machine_mode mode, rtx operands[]) argument
9572 ix86_fixup_binary_operands(enum rtx_code code, enum machine_mode mode, rtx operands[]) argument
9631 ix86_fixup_binary_operands_no_copy(enum rtx_code code, enum machine_mode mode, rtx operands[]) argument
9643 ix86_expand_binary_operator(enum rtx_code code, enum machine_mode mode, rtx operands[]) argument
9677 ix86_binary_operator_ok(enum rtx_code code, enum machine_mode mode ATTRIBUTE_UNUSED, rtx operands[3]) argument
9707 ix86_expand_unary_operator(enum rtx_code code, enum machine_mode mode, rtx operands[]) argument
9821 ix86_expand_fp_absneg_operator(enum rtx_code code, enum machine_mode mode, rtx operands[]) argument
9889 ix86_expand_copysign(rtx operands[]) argument
9943 ix86_split_copysign_const(rtx operands[]) argument
9971 ix86_split_copysign_var(rtx operands[]) argument
11188 ix86_expand_int_movcc(rtx operands[]) argument
11887 ix86_expand_fp_movcc(rtx operands[]) argument
11973 ix86_expand_fp_vcond(rtx operands[]) argument
11996 ix86_expand_int_vcond(rtx operands[]) argument
12101 ix86_expand_int_addcc(rtx operands[]) argument
12341 ix86_split_long_move(rtx operands[]) argument
12593 ix86_split_ashl(rtx *operands, rtx scratch, enum machine_mode mode) argument
12720 ix86_split_ashr(rtx *operands, rtx scratch, enum machine_mode mode) argument
12799 ix86_split_lshr(rtx *operands, rtx scratch, enum machine_mode mode) argument
17267 rtx operands[2]; local
18751 x86_emit_floatuns(rtx operands[2]) argument
19702 output_387_reg_move(rtx insn, rtx *operands) argument
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/freebsd-10.0-release/contrib/gcc/config/arm/
H A Darm.c715 /* Emit an insn that's a simple single-set. Both the operands must be known
3108 rtl operands. CALL_SYMBOL is used to distinguish between
4723 /* It's just the cost of the two operands. */
4752 /* It's just the cost of the two operands. */
5185 on precisely how certain input operands are used. */
5208 /* Iterate over all the operands in DEP. If we write an operand
5837 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5850 /* Loop over the operands and check that the memory references are
5860 if (GET_CODE (operands[nops + i]) == SUBREG)
5861 operands[nop
5826 load_multiple_sequence(rtx *operands, int nops, int *regs, int *base, HOST_WIDE_INT *load_offset) argument
5995 emit_ldm_seq(rtx *operands, int nops) argument
6053 store_multiple_sequence(rtx *operands, int nops, int *regs, int *base, HOST_WIDE_INT * load_offset) argument
6184 emit_stm_seq(rtx *operands, int nops) argument
6383 arm_gen_movmemqi(rtx *operands) argument
6830 arm_reload_in_hi(rtx *operands) argument
6946 arm_reload_out_hi(rtx *operands) argument
8459 vfp_output_fstmx(rtx * operands) argument
8560 output_call(rtx *operands) argument
8583 output_call_mem(rtx *operands) argument
8622 output_mov_long_double_fpa_from_arm(rtx *operands) argument
8643 output_mov_long_double_arm_from_fpa(rtx *operands) argument
8663 output_mov_long_double_arm_from_arm(rtx *operands) argument
8698 output_mov_double_fpa_from_arm(rtx *operands) argument
8716 output_mov_double_arm_from_fpa(rtx *operands) argument
8734 output_move_double(rtx *operands) argument
9021 output_add_immediate(rtx *operands) argument
9047 output_multi_immediate(rtx *operands, const char *instr1, const char *instr2, int immed_op, HOST_WIDE_INT n) argument
9834 rtx operands[3]; local
14160 thumb_load_double_from_address(rtx *operands) argument
14271 thumb_output_move_mem_multiple(int n, rtx *operands) argument
14352 thumb_expand_movmemqi(rtx *operands) argument
14402 thumb_reload_out_hi(rtx *operands) argument
14878 arm_output_load_gr(rtx *operands) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.h40 // meanings of its operands.
49 // register, for instance). Given this information, the operands can be
53 // and operands into a format understandable by the client - in this case, an
78 uint16_t operands;
/freebsd-10.0-release/contrib/gcc/config/sparc/
H A Dsparc.c258 /* Save the operands last given to a compare for use when we
924 sparc_expand_move (enum machine_mode mode, rtx *operands)
927 if (GET_CODE (operands[0]) == MEM)
930 if (register_or_zero_operand (operands[1], mode))
935 operands[0] = validize_mem (operands[0]);
936 operands[1] = force_reg (mode, operands[1]);
942 && CONSTANT_P (operands[1])
943 && GET_CODE (operands[
920 sparc_expand_move(enum machine_mode mode, rtx *operands) argument
2038 gen_v9_scc(enum rtx_code compare_code, register rtx *operands) argument
2155 emit_soft_tfmode_libcall(const char *func_name, int nargs, rtx *operands) argument
2238 emit_soft_tfmode_binop(enum rtx_code code, rtx *operands) argument
2264 emit_soft_tfmode_unop(enum rtx_code code, rtx *operands) argument
2275 emit_soft_tfmode_cvt(enum rtx_code code, rtx *operands) argument
2376 emit_hard_tfmode_operation(enum rtx_code code, rtx *operands) argument
2405 emit_tfmode_binop(enum rtx_code code, rtx *operands) argument
2414 emit_tfmode_unop(enum rtx_code code, rtx *operands) argument
2423 emit_tfmode_cvt(enum rtx_code code, rtx *operands) argument
4098 rtx operands[3]; local
4219 rtx operands[1]; local
6147 sparc_emit_floatunsdi(rtx *operands, enum machine_mode mode) argument
6180 sparc_emit_fixunsdi(rtx *operands, enum machine_mode mode) argument
7666 output_v8plus_shift(rtx *operands, rtx insn, const char *opcode) argument
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/freebsd-10.0-release/contrib/binutils/gas/
H A Ditbl-ops.h84 unsigned long itbl_assemble (char *name, char *operands);
/freebsd-10.0-release/contrib/gdb/include/
H A Dxtensa-isa-internal.h31 /* Encode/decode function types for immediate operands. */
68 int num_operands; /* Size of "operands" array. */
69 xtensa_operand_internal **operands; /* Array of operand structures. */ member in struct:xtensa_iclass_internal_struct

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