Searched refs:isReg (Results 1 - 25 of 152) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DMachineOperand.h188 return isReg() ? 0 : SubReg_TargetFlags;
191 assert(!isReg() && "Register operands can't have target flags");
196 assert(!isReg() && "Register operands can't have target flags");
223 /// isReg - Tests if this is a MO_Register operand.
224 bool isReg() const { return OpKind == MO_Register; } function in class:llvm::MachineOperand
260 assert(isReg() && "This is not a register operand!");
265 assert(isReg() && "Wrong MachineOperand accessor");
270 assert(isReg() && "Wrong MachineOperand accessor");
275 assert(isReg() && "Wrong MachineOperand accessor");
280 assert(isReg()
[all...]
H A DLiveVariables.h215 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
251 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp109 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
131 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
142 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
153 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
165 assert(MI.getOperand(OpNo+1).isReg());
183 assert(MI.getOperand(OpNo+1).isReg());
200 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
225 if (MO.isReg()) {
/freebsd-10.0-release/contrib/llvm/include/llvm/MC/MCParser/
H A DMCParsedAsmOperand.h47 /// isReg - Is this a register operand?
48 virtual bool isReg() const = 0;
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DAntiDepBreaker.h64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
H A DDeadMachineInstructionElim.cpp68 if (MO.isReg() && MO.isDef()) {
125 if (!MO.isReg() || !MO.isDef())
154 if (MO.isReg() && MO.isDef()) {
173 if (MO.isReg() && MO.isUse()) {
H A DMachineInstr.cpp92 assert(isReg() && "Wrong MachineOperand accessor");
113 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
116 if (isReg() && isOnRegUseList())
139 bool WasReg = isReg();
580 if (Operands[i].isReg())
589 if (Operands[i].isReg())
642 bool isImpReg = Op.isReg() && Op.isImplicit();
644 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
686 if (NewMO->isReg()) {
721 if (Operands[i].isReg())
[all...]
H A DProcessImplicitDefs.cpp71 if (MO->isReg() && MO->isUse() && MO->readsReg())
106 if (!MO->isReg())
H A DTargetInstrInfo.cpp122 if (HasDef && !MI->getOperand(0).isReg())
133 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
192 if (!MI->getOperand(SrcOpIdx1).isReg() ||
193 !MI->getOperand(SrcOpIdx2).isReg())
227 if (MO.isReg()) {
442 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
480 if (!MO.isReg()) continue;
H A DMachineInstrBundle.cpp54 if (MO.isReg() && MO.isInternalRead())
126 if (!MO.isReg())
257 if (!MO.isReg() || MO.getReg() != Reg)
294 if (!MO.isReg())
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinterDwarf.cpp180 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
188 } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
189 assert(Dst.isReg() && "Machine move not supported yet.");
192 assert(!Dst.isReg() && "Machine move not supported yet.");
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCCodeEmitter.cpp184 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
200 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
209 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
219 assert(MI.getOperand(OpNo+1).isReg());
235 assert(MI.getOperand(OpNo+1).isReg());
257 if (MO.isReg()) {
H A DPPCCTRLoops.cpp154 bool isReg() const { return Kind == CV_Register; } function in class:__anon2461::CountValue
159 assert(isReg() && "Wrong CountValue accessor");
177 if (isReg()) { OS << PrintReg(getReg()); }
391 assert(InitialValue->isReg() && "Expecting register for init value");
464 MI->getOperand(1).isReg() && // could be a frame index instead
481 if (MO.isReg() && MO.isDef() &&
516 if (MO.isReg() && MO.isDef()) {
530 if (OPO.isReg() && OPO.isDef()) {
573 if (!MO.isReg() || !MO.isDef())
683 if (TripCount->isReg()) {
[all...]
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp252 bool isReg() const { return Kind == CV_Register; } function in class:__anon2395::CountValue
256 assert(isReg() && "Wrong CountValue accessor");
260 assert(isReg() && "Wrong CountValue accessor");
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
527 if (Op1.isReg()) {
564 if (InitialValue->isReg()) {
591 if (InitialValue->isReg()) {
598 if (EndValue->isReg()) {
624 if (Start->isReg()) {
629 if (End->isReg()) {
[all...]
H A DHexagonNewValueJump.cpp150 if (II->getOperand(i).isReg() &&
474 MI->getOperand(0).isReg() &&
482 isSecondOpReg = MI->getOperand(2).isReg();
516 if (MI->getOperand(0).isReg() &&
573 if (MO.isReg() && MO.isUse()) {
580 if (localMO.isReg() && localMO.isUse() &&
634 if (cmpInstr->getOperand(0).isReg() &&
637 if (cmpInstr->getOperand(1).isReg() &&
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp34 assert(MI->getNumOperands() == 4 && MI->getOperand(0).isReg()
47 if (!MO.isReg())
70 } else if (MO.isReg()) {
269 assert(MO.isReg() && "unexpected inline assembly memory operand");
284 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
/freebsd-10.0-release/contrib/llvm/include/llvm/MC/
H A DMCInst.h56 bool isReg() const { return Kind == kRegister; } function in class:llvm::MCOperand
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
H A DMachineLocation.h54 bool isReg() const { return IsRegister; } function in class:llvm::MachineLocation
/freebsd-10.0-release/contrib/llvm/lib/MC/
H A DMCInst.cpp22 else if (isReg())
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/InstPrinter/
H A DMBlazeInstPrinter.cpp38 if (Op.isReg()) {
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/
H A DMBlazeDelaySlotFiller.cpp134 bool aop_is_reg = a->getOperand(aop).isReg();
142 bool mop_is_reg = m->getOperand(mop).isReg();
162 if (a->getOperand(aop).isReg()) {
166 if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit()) {
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DSIInsertWaits.cpp137 assert(Op.isReg() && "First LGKM operand must be a register!");
153 if (!Op.isReg())
172 if (I->isReg() && I->isUse())
181 if (!Op.isReg())
/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp213 if (!MO.isReg())
244 assert(Reg.isReg() && "JMPL first operand is not a register.");
251 assert(RegOrImm.isReg() && "JMPLrr second operand is not a register.");
265 if (!MO.isReg())
/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/InstPrinter/
H A DXCoreInstPrinter.cpp74 if (Op.isReg()) {
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/InstPrinter/
H A DMSP430InstPrinter.cpp49 if (Op.isReg()) {

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